Patents by Inventor Shinpei Ishida

Shinpei Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9349694
    Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsunori Shibuya, Soichi Homma, Yuusuke Takano, Shinpei Ishida
  • Publication number: 20150171019
    Abstract: According to one embodiment, a semiconductor device includes a substrate. A semiconductor chip is disposed on a first surface of the substrate. The semiconductor chip is covered with a sealing material. A front surface and a side surface of the sealing material are covered with a conductive film. On an outer edge of a substrate-side of the semiconductor device, a step or a trench is formed.
    Type: Application
    Filed: August 29, 2014
    Publication date: June 18, 2015
    Inventors: Katsunori SHIBUYA, Soichi HOMMA, Yuusuke TAKANO, Shinpei ISHIDA
  • Patent number: 7009303
    Abstract: Disclosed here is a multi-chip module enhanced in performance and reduced in size. A second semiconductor chip having bonding pads at the periphery of its surface is mounted over a first semiconductor chip laid out over a surface of a substrate back to back and a spacer is provided at a portion of the second semiconductor chip surface except for a predetermined area that includes the portion where the bonding pads are formed while a third semiconductor chip is mounted over the spacer, the third semiconductor having the same circuit function as the second semiconductor chip and oriented similarly to the second semiconductor chip. The bonding pads of the second and third semiconductor chips are connected to their corresponding electrodes formed over the substrate through bonding wires respectively, then the first to third semiconductor chips and the bonding wires provided over the substrate are all sealed by a sealing agent.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: March 7, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kuroda, Shinpei Ishida
  • Publication number: 20050104183
    Abstract: Disclosed here is a multi-chip module enhanced in performance and reduced in size. A second semiconductor chip having bonding pads at the periphery of its surface is mounted over a first semiconductor chip laid out over a surface of a substrate back to back and a spacer is provided at a portion of the second semiconductor chip surface except for a predetermined area that includes the portion where the bonding pads are formed while a third semiconductor chip is mounted over the spacer, the third semiconductor having the same circuit function as the second semiconductor chip and oriented similarly to the second semiconductor chip. The bonding pads of the second and third semiconductor chips are connected to their corresponding electrodes formed over the substrate through bonding wires respectively, then the first to third semiconductor chips and the bonding wires provided over the substrate are all sealed by a sealing agent.
    Type: Application
    Filed: October 25, 2004
    Publication date: May 19, 2005
    Inventors: Hiroshi Kuroda, Shinpei Ishida