Abstract: Provided is a circuit module reduced in size. The circuit module includes: a substrate to which electronic parts are mounted; a shield case; and a bonding material for bonding the substrate and the shield case. The shield case includes legs extending from given side walls of the shield case to overlap with portions of the side faces of the substrate, and the portions of the side faces of the substrate are bonded to the legs of the shield case by the bonding material. The shield case includes openings formed in the given side walls of the shield case to expose overlapping portions where the portions of the side faces of the substrate overlap with the legs of the shield case.

Abstract: A mixer circuit 1 is a mixer circuit including a pair of differential transistors which receives an input signal IN1-IN2; and a serial resonance circuit 2 connected between collectors of transistors Q1 and Q2 of the pair of differential transistors, the mixer circuit mixing the input signal IN1-IN2 and a local signal LO1-LO2, and outputting the mixed signal.

Abstract: The reception system of the present invention includes a detection circuit serving as detecting means for detecting that the strength of the receiver signal is equal to or greater than a predetermined value, and a resetting circuit serving as resetting means for, under instruction of the detection circuit, immediately increasing power consumption of the reception section when the detection circuit detects a large signal so as to bring back the state where the reception system ensures the greatest power consumption amount for the entire system and the sufficiently-desirable system performance. Consequently, this invention provides an effect of reducing power consumption amount of the entire system, and an effect of stable reception by preventing reception failure even when a large interfering signal is suddenly supplied due to a change in peripheral radio wave condition.

Abstract: An example wireless communication device is provided with a binarizing circuit which precisely carries out binarization even if a level of an input signal is kept substantially consistent for a long period. The binarizing circuit includes: a comparator which outputs a data slicer output by comparing a generated signal generated from a demodulated signal with 0 level; a feedback circuit which detects a direct current level of the generated signal, thereby outputting an inversion signal of the direct current level; and an adder circuit which outputs the generated signal by adding the inversion signal to the demodulated signal. Since an offset canceller of the feedback circuit outputs 0 to an integration circuit when the generated signal falls within a predetermined range, the generated signal does not follow the demodulated signal even if the demodulated signal is kept at a substantially consistent level, thereby reducing errors.

Abstract: A receiving apparatus may be provided with a variable gain amplifier amplifying a received signal, an output level of which is detected by a level detection circuit. A comparing circuit compares an output from a level detection circuit to a reference level. There is a binarizing circuit and a detection circuit for detecting a switching of a gain of a variable gain amplifier. A slice level holding circuit holds, at substantially constant value, a slice level employed at the binarizing circuit. A counter circuit and at least one of the slice levels may be held at substantially constant value for a prescribed time when switching of the gain of a variable gain amplifier is detected, rendering at least partially ineffective any noise produced during switching of the gain of the variable gain amplifier.

Abstract: A receiving apparatus may be provided with variable gain amplifier(s) 5 amplifying received signal(s), output level(s) of which is or are detected by level detection circuit(s) 6; comparing circuit(s) 7 comparing output(s) from level detection circuit(s) 6 to reference level(s); binarizing circuit(s) 12; detection circuit(s) detecting switching of gain(s) of variable gain amplifier(s) 5; slice level holding circuit(s) 14 holding, at substantially constant value(s), slice level(s) employed at binarizing circuit(s) 12; counter circuit(s) 16; and so forth; and at least one of the slice level(s) may be held at substantially constant value(s) for prescribed time(s) when switching of gain(s) of variable gain amplifier(s) 5 is detected, rendering at least partially ineffective any noise produced during switching of gain(s) of variable gain amplifier(s) 5.

Abstract: A wireless communication device of the present invention is provided with a binarizing circuit which precisely carries out binarization even if a level of an input signal is kept substantially consistent for a long period. The binarizing circuit includes: a comparator which outputs a data slicer output by comparing a generated signal generated from a demodulated signal with 0 level; a feedback circuit which detects a direct current level of the generated signal, thereby outputting an inversion signal of the direct current level; and an adder circuit which outputs the generated signal by adding the inversion signal to the demodulated signal. Since an offset canceller of the feedback circuit outputs 0 to an integration circuit when the generated signal falls within a predetermined range, the generated signal does not follow the demodulated signal even if the demodulated signal is kept at a substantially consistent level, thereby preventing the errors.