Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Abstract: A processor and an instruction scheduling method for X-channel interleaved multi-threading, where X is an integer greater than one. The processor includes a decoding unit and a processing unit. The decoding unit is configured to obtain one instruction from each of Z predefined threads in each cyclic period, decode the Z obtained instructions to obtain Z decoding results, and send the Z decoding results to the processing unit, where each cyclic period includes X sending periods, one decoding result is sent to the processing unit in each sending period, a decoding result of the Z decoding results may be repeatedly sent by the decoding unit in a plurality of sending periods, wherein 1?Z<X or Z=X, and wherein Z is an integer. The processing unit (32) is configured to execute the instruction based on the decoding result.

Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Abstract: A processor and an instruction scheduling method for X-channel interleaved multi-threading, where X is an integer greater than one. The processor includes a decoding unit and a processing unit. The decoding unit is configured to obtain one instruction from each of Z predefined threads in each cyclic period, decode the Z obtained instructions to obtain Z decoding results, and send the Z decoding results to the processing unit, where each cyclic period includes X sending periods, one decoding result is sent to the processing unit in each sending period, a decoding result of the Z decoding results may be repeatedly sent by the decoding unit in a plurality of sending periods, wherein 1?Z?X or Z=X, and wherein Z is an integer. The processing unit (32) is configured to execute the instruction based on the decoding result.

Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.

Abstract: A vector processor includes a plurality of execution units arranged in parallel, a register file, and a plurality of load units. The register file includes a plurality of registers coupled to the execution units. Each of the load units is configured to load, in a single transaction, a plurality of the registers with data retrieved from memory. The loaded registers corresponding to different execution units. Each of the load units is configured to distribute the data to the registers in accordance with an instruction selectable distribution. The instruction selectable distribution specifies one of plurality of distributions. Each of the distributions specifies a data sequence that differs from the sequence in which the data is stored in memory.

Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage, and pass vector instructions in the instruction stream to the vector coprocessor core. The vector coprocessor core includes a register file, a plurality of execution units, and a table lookup unit. The register file includes a plurality of registers. The execution units are arranged in parallel to process a plurality of data values. The execution units are coupled to the register file. The table lookup unit is coupled to the register file in parallel with the execution units. The table lookup unit is configured to retrieve table values from one or more lookup tables stored in memory by executing table lookup vector instructions in a table lookup loop.

Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core is configured to retrieve an instruction stream from program storage. The instruction stream includes scalar instructions executable by the scalar processor core and vector instructions executable by the vector coprocessor core. The scalar processor core is configured to pass the vector instructions to the vector coprocessor core. The vector coprocessor core configured to process a plurality of data values in parallel while executing each vector instruction passed by the scalar processor core. The vector coprocessor core includes a plurality of processing paths arranged in parallel to process the data values. Each of the processing paths includes an execution unit. Each of the execution units is configured to communicate a result of processing to each other of the execution units.

Abstract: A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: Color filter array demosaicing as is useful in digital cameras, still and video, using a single sensor includes blending of directional and non-directional interpolations. Directional interpolation uses edge detection with lowpass filtering with neighboring pixels for erroneous detection correction.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: Digital Camera includes separate preview engine, burst mode compression/decompression engine, image pipeline, CCD plus CCD controller, and memory plus memory controller. ARM microprocessor and DSP share control, and preview engine register provide parameters for preview engine image processing hardware.

Abstract: A synchronization detection circuit quickly detects resynchronization to a new input signal quickly when the input signal changes, etc. A frame synchronization detection circuit 3 synchronizes the frame pattern contained in, for example, the MUSE signal, etc., and a frame synchronizing signal (signal (IFP1)) formed in the MUSE decoder, pattern detection circuits 30, an integrating circuit 32, and a slicing circuit 36 function in concert to detect and output the frame pattern to a phase comparator 36 as a signal (SS).

Abstract: A synchronizing signal creating circuit which can feed stable synchronizing signals even after input signals stop. it is constituted of gate circuit 804 makes signal (G) into logic level 1 and outputs to switching circuit 818 when the still picture creating apparatus which executes processing with the synchronizing signals created by synchronizing signal creating circuit 80 executes creation or output of still pictures, and when frame synchronizing signal (IFP) and the frame pulse do not synchronize. Switching circuit 818 selects contact point b and outputs numerical value (V.sub.DC) to digital/analog converting circuit 816 so the operation of PLL loop stops. Consequently, in this case, voltage control oscillating circuit 820 creates signals (HCK) with a frequency corresponding to numerical value (V.sub.DC) and in other cases, creates signals (HCK) with a frequency determined by the operation of the PLL loop.

Abstract: A noise reduction circuit for use with video signals or image producing signals in which trailing and other image degrading phenomena are prevented by not using the noise reduction circuit for the edge of the motion picture portion on the image. The noise reduction circuit includes a subtractor 14 which outputs a difference signal E between input video signal VSi and delayed video signal VSd. ROM 18, a look-up table that forms the coefficient multiplier, outputs a corrected difference signal KE corresponding to the difference signal E from subtractor 14. At adder 12, corrected difference signal KE from ROM 18 is added to input video signal VSi, forming output video signal VSo processed by the noise reduction processing. However, when "H" level expansion video signal MEH,Y is output from vertical expansion circuit 42, the outputs of AND gates 24, 26 become null, and the output signal of ROM 18 becomes null.

Abstract: A still picture generating apparatus which can create still pictures without deterioration in the picture quality from MUSE signals having a frame memory 32 for executing motion compensation by moving the position of the stored data by signals MVH and MVV and executes frame insertion processing by functioning together with switch 30. When the freeze operation is carried out, switch 30 selects the contact point a side and freeze encoder 62 outputs the motion vector as is in the first timing period, a signal which is half the motion vector in the second timing period, and numerical value 0 in the third timing period to frame memory 32 as signals MVH and MVV. By the operation, the positions of the data of two fields stored in frame memory 32 are superimposed by being frame inserted by the aforementioned operation and still pictures are created by executing a prescribed process.

Abstract: A motion detecting circuit and a noise reducing circuit of high reliability and independent of the magnitude of motion, presence/absence of noise, and magnitude of the noise. The motion detecting circuit includes a subtractor 14 which receives as inputs, an input video signal VS.sub.i from an input terminal 10 and a delayed video signal VS.sub.d delayed by one picture unit (one frame in the case of the NTSC format) from a frame memory 12. The difference between the two signals VS.sub.i and VS.sub.d is taken and a difference signal e is output for each pixel of a video display.