Patents by Inventor Shinro Ikeda

Shinro Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7026179
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x?0.011 and x?450 ?m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H?70×10?4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos?1(1?HCZ), where C (cm?1) is the proportionality constant when the radius of curvature of the substrate ? (cm) is expressed as 1/?=CZ.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: April 11, 2006
    Assignee: Sony Corporation
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Publication number: 20050191773
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x?0.011 and x?450 ?m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H?70×10?4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos?1(1?HCZ), where C (cm?1) is the proportionality constant when the radius of curvature of the substrate ? (cm) is expressed as 1/?=CZ.
    Type: Application
    Filed: June 23, 2004
    Publication date: September 1, 2005
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Publication number: 20050098791
    Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 12, 2005
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima, Shinro Ikeda, Katsuyoshi Shibuya, Yasuhiko Suzuki
  • Patent number: 6890785
    Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: May 10, 2005
    Assignee: Sony Corporation
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima, Shinro Ikeda, Katsuyoshi Shibuya, Yasuhiko Suzuki
  • Publication number: 20050000407
    Abstract: A semiconductor laser, a semiconductor device and a nitride series III-V group compound substrate capable of obtaining a crystal growth layer with less fluctuation of the crystallographic axes and capable of improving the device characteristics, as well as a manufacturing method therefor are provided. The semiconductor laser comprises, on one surface of a substrate used for growing, a plurality of spaced apart seed crystal layers and an n-side contact layer having a lateral growing region which is grown on the basis of the plurality of seed crystal layers. The seed crystal layer is formed in that a product of width w1 (unit: ?m) at the boundary thereof relative to the n-side contact layer along the arranging direction A and a thickness t1 (unit: ?m) along the direction of laminating the n-side contact layer is 15 or less. This can decrease the fluctuation of the crystallographic axes in the n-side contact layer.
    Type: Application
    Filed: August 2, 2004
    Publication date: January 6, 2005
    Inventors: Motonobu Takeya, Katsunori Yanashima, Takeharu Asano, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya, Tomonori Hino, Satoru Kijima, Masao Ikeda
  • Patent number: 6836498
    Abstract: A semiconductor laser, a semiconductor device and a nitride series III-V group compound substrate capable of obtaining a crystal growth layer with less fluctuation of the crystallographic axes and capable of improving the device characteristics, as well as a manufacturing method therefor are provided. The semiconductor laser comprises, on one surface of a substrate used for growing, a plurality of spaced apart seed crystal layers and an n-side contact layer having a lateral growing region which is grown on the basis of the plurality of seed crystal layers. The seed crystal layer is formed in that a product of width w1 (unit: &mgr;m) at the boundary thereof relative to the n-side contact layer along the arranging direction A and a thickness t1 (unit: &mgr;m) along the direction of laminating the n-side contact layer is 15 or less. A semiconductor layer comprising a nitride series III-V group compound semiconductor is laminated on a substrate 11 comprising an n-type GaN.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: December 28, 2004
    Assignee: Sony Corporation
    Inventors: Motonobu Takeya, Katsunori Yanashima, Takeharu Asano, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya, Tomonori Hino, Satoru Kijima, Masao Ikeda
  • Patent number: 6829270
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x≦0.011 and x≧450 &mgr;m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H≦70×10−4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos−1(1−HCZ), where C (cm−1) is the proportionality constant when the radius of curvature of the substrate &rgr; (cm) is expressed as 1/&rgr;=CZ.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: December 7, 2004
    Assignee: Sony Corporation
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Publication number: 20030227026
    Abstract: A nitride semiconductor having a large low-defect region in a surface thereof, and a semiconductor device using the same are provided. Also, a manufacturing method for a nitride semiconductor comprising a layer formation step using a transverse growth technique where surface defects can easily be reduced, and a manufacturing method for a semiconductor device using the same are provided. On a substrate, a seed crystal part is formed in a stripe pattern with a buffer layer in between. Next, crystals are grown from the seed crystal part in two stages of growth conditions to form a nitride semiconductor layer. Low temperature growing parts with a trapezoid shaped cross section are formed at a growth temperature of 1030° C. in the first stage and a transverse growth is dominantly advanced at a growth temperature of 1070° C. to form a high temperature growing part between the low temperature growing parts in the second stage.
    Type: Application
    Filed: February 24, 2003
    Publication date: December 11, 2003
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima, Shinro Ikeda, Katsuyoshi Shibuya, Yasuhiko Suzuki
  • Publication number: 20030045103
    Abstract: When GaN or other nitride III-V compound semiconductor layers are grown on a substrate such as a sapphire substrate, thickness x of the substrate relative to thickness y of the nitride III-V compound semiconductor layers is controlled to satisfy 0<y/x≦0.011 and x≧450 &mgr;m. Alternatively, if the maximum dimension of the substrate is D (cm), its warpage H is in the range of 0<H≦70×10−4 (cm), and Z=y/x, D is controlled to satisfy the relation 0<D<(2/CZ)cos−1(1-HCZ), where C (cm−1) is the proportionality constant when the radius of curvature of the substrate &rgr; (cm) is expressed as 1/&rgr;=CZ.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 6, 2003
    Inventors: Yasuhiko Suzuki, Takeharu Asano, Motonobu Takeya, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya
  • Patent number: 6509579
    Abstract: To provide a semiconductor device capable of preventing the bowing of the substrate, and having a semiconductor layer of a III-V group compound of a nitride system with excellent crystallinity. The semiconductor layer of the III-V group compound of the nitride system whose thickness is equal to or less than 8 &mgr;m, is provided onto a substrate made of sapphire. This reduces the bowing of the substrate due to differences in a thermal expansion coefficient and a lattice constant between the substrate and the semiconductor layer of the III-V group compound of the nitride system. An n-side contact layer forming the semiconductor layer of the III-V group of the nitride system has partially a lateral growth region made by growing in a lateral direction from a crystalline part of a seed crystal layer. In the lateral growth region, dislocation density restricts low, therefore, regions corresponding to the lateral growth region of each layer formed onto the n-side contact layer has excellent crystallinity.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: January 21, 2003
    Assignee: Sony Corporation
    Inventors: Motonobu Takeya, Katsunori Yanashima, Masao Ikeda, Takeharu Asano, Shinro Ikeda, Tomonori Hino, Katsuyoshi Shibuya
  • Publication number: 20020064195
    Abstract: A semiconductor laser, a semiconductor device and a nitride series III-V group compound substrate capable of obtaining a crystal growth layer with less fluctuation of the crystallographic axes and capable of improving the device characteristics, as well as a manufacturing method therefor are provided. The semiconductor laser comprises, on one surface of a substrate used for growing, a plurality of spaced apart seed crystal layers and an n-side contact layer having a lateral growing region which is grown on the basis of the plurality of seed crystal layers. The seed crystal layer is formed in that a product of width w1 (unit: &mgr;m) at the boundary thereof relative to the n-side contact layer along the arranging direction A and a thickness t1 (unit: &mgr;m) along the direction of laminating the n-side contact layer is 15 or less.
    Type: Application
    Filed: June 5, 2001
    Publication date: May 30, 2002
    Inventors: Motonobu Takeya, Katsunori Yanashima, Takeharu Asano, Osamu Goto, Shinro Ikeda, Katsuyoshi Shibuya, Tomonori Hino, Satoru Kijima, Masao Ikeda
  • Publication number: 20010035534
    Abstract: To provide a semiconductor device capable of preventing the bowing of the substrate, and having a semiconductor layer of a III-V group compound of a nitride system with excellent crystallinity.
    Type: Application
    Filed: January 16, 2001
    Publication date: November 1, 2001
    Inventors: Motonobu Takeya, Katsunori Yanashima, Masao Ikeda, Takeharu Asano, Shinro Ikeda, Tomonori Hino, Katsuyoshi Shibuya
  • Publication number: 20010025989
    Abstract: To provide a semiconductor device capable of enhancing crystallinity of a semiconductor of a III-V group compound of a nitride system formed on a sapphire substrate and to provide a method of manufacturing the same.
    Type: Application
    Filed: January 12, 2001
    Publication date: October 4, 2001
    Inventors: Katsuyoshi Shibuya, Takeharu Asano, Satoru Kijima, Katsunori Yanashima, Motonobu Takeya, Masao Ikeda, Tomonori Hino, Takashi Yamaguchi, Shinro Ikeda, Osamu Goto