Abstract: A printing system includes a terminal device that generates print job data, and a child printer that is configured to communicate with a parent printer that receives the print job data from the terminal device, where the child printer is configured to perform printing based on the print job data. The terminal device stores the generated print job data and transmits, to the parent printer, print job related data including the stored print job data and a plurality of pieces of access information for accessing the terminal device. The child printer requests a transmission of the print job data from the terminal device based on the plurality of pieces of access information included in the print job related data received by the parent printer.

Abstract: A printing system includes a terminal device that generates print job data, and a child printer that is configured to communicate with a parent printer that receives the print job data from the terminal device, where the child printer is configured to perform printing based on the print job data. The terminal device stores the generated print job data and transmits, to the parent printer, print job related data including the stored print job data and a plurality of pieces of access information for accessing the terminal device. The child printer requests a transmission of the print job data from the terminal device based on the plurality of pieces of access information included in the print job related data received by the parent printer.

Abstract: There is provided an error determination program executed by an information processor included in an electronic apparatus that includes a device installation section capable of installing any one of a plurality of devices having different formats, a host controller acting as an intermediary between the information processor and the device installed in the device installation section, and a storage circuit storing an error determination information table that includes a plurality of pieces of error determination information for determining a presence or absence of any error in a plurality of responses to a plurality of commands from the devices installable in the device installation section, by associating the pieces of error determination information with a combination of the formats of the installable devices and the commands executable by the devices.

Abstract: There is provided an error determination program executed by an information processor included in an electronic apparatus that includes a device installation section capable of installing any one of a plurality of devices having different formats, a host controller acting as an intermediary between the information processor and the device installed in the device installation section, and a storage circuit storing an error determination information table that includes a plurality of pieces of error determination information for determining a presence or absence of any error in a plurality of responses to a plurality of commands from the devices installable in the device installation section, by associating the pieces of error determination information with a combination of the formats of the installable devices and the commands executable by the devices.

Abstract: A host device for controlling a storage device controller to access a storage device includes: a command issue controller controlling an issue of a command for allowing the storage device controller to access the storage device; a response detector for detecting a reception of a response from the storage device corresponding to the command; and a buffer data controller controlling reading and writing of a buffer of the storage device controller. The buffer stores one of reading data and writing data of the storage device. The buffer data controller controls one of the reading and the writing at least once in a predetermined data size unit corresponding to the command after the command issue controller issues the command.

Abstract: When transfer condition information is set and the start of automatic control transfer is instructed, a transfer controller (host controller) automatically issues a setup stage transaction and automatically transfers a setup stage packet, then, if there is data to be transferred, it automatically issues a data stage transaction and automatically transfers a data stage packet. It then automatically issues a status stage transaction and automatically transfers a status stage packet. Device request data, the total size of transfer data, data stage present/absent information, transfer direction in the data stage, and maximum packet size are set in transfer condition registers. A pipe region is allocated in the packet buffer during host operation of USB On-The-Go.

Abstract: Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.

Abstract: A data transfer control device for data transfer through a bus, includes: a buffer controller which controls access to a packet buffer which stores data; and a transfer controller which controls transfer of the data stored in the packet buffer. A transaction for performing data transfer with a transfer destination is issued, and when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A signal state detection circuit of a data transfer control device notifies a processing of results detected by a line state detection circuit or a power supply line detection circuit by using an interrupt signal. The processing sets a state command corresponding to a state of a transition destination judged based on the notified detection results in a control register of a state controller. A state command decoder decodes the state command set in the control register and generates a control signal. A signal line control circuit controls a signal state of at least one of signal lines formed of data signal lines (D+ and D?) and power supply lines (VBUS and GND) based on the control signal.

Abstract: A data transfer control device for data transfer through a bus, includes: a buffer controller which controls access to a packet buffer which stores data; and a transfer controller which controls transfer of the data stored in the packet buffer. A transaction for performing data transfer with a transfer destination is issued, and when a negative acknowledgment (NAK) response to the issued transaction is returned from the transfer destination, issuance of a retransmission transaction for the NAK response is allowed after waiting for a predetermined skip timing.

Abstract: When transfer condition information is set and the start of automatic control transfer is instructed, a transfer controller (host controller) automatically issues a setup stage transaction and automatically transfers a setup stage packet, then, if there is data to be transferred, it automatically issues a data stage transaction and automatically transfers a data stage packet. It then automatically issues a status stage transaction and automatically transfers a status stage packet. Device request data, the total size of transfer data, data stage present/absent information, transfer direction in the data stage, and maximum packet size are set in transfer condition registers. A pipe region is allocated in the packet buffer during host operation of USB On-The-Go.

Abstract: Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.

Abstract: A plurality of pipe regions PIPE0 to PIPEe in which data transferred to and from endpoints is stored are allocated in a packet buffer (FIFO). Transfer condition information on data transfer between the pipe regions and the endpoints is set in transfer condition registers TREG0 to TREGe in a register section. A host (transfer) controller automatically generates a transaction for each of the endpoints based on the transfer condition information (total size, maximum packet size, transfer direction, number of continuous execution times, token issue interval, and the like) set in the transfer condition registers, and automatically transfers data between each pipe region and the endpoint. An OTG (state) controller which controls a state of USB On-The-Go is provided. The pipe regions are allocated in the packet buffer during a host operation.

Abstract: A signal state detection circuit of a data transfer control device notifies a processing of results detected by a line state detection circuit or a power supply line detection circuit by using an interrupt signal. The processing sets a state command corresponding to a state of a transition destination judged based on the notified detection results in a control register of a state controller. A state command decoder decodes the state command set in the control register and generates a control signal. A signal line control circuit controls a signal state of at least one of signal lines formed of data signal lines (D+ and D−) and power supply lines (VBUS and GND) based on the control signal.