Patents by Inventor Shinsuke Nakajyo

Shinsuke Nakajyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040235271
    Abstract: A method of manufacturing semiconductor device in the method of manufacturing wafer level semiconductor device that can search the defective products from the marking information even when sealing resin is formed on the wafer and a semiconductor device manufactured with the same method. A method of manufacturing wafer level semiconductor comprises a process to seal with a resin material the surface of wafer having the front surface and rear surface and forming a plurality of semiconductor chips on the front surface, a first marking process for marking the position information corresponding to each chip to the region of each chip at the rear surface of the wafer, a process for performing the electrical test to each chip, a second marking process for marking the result of the electrical test to the region of each chip at the rear surface of the wafer and a dicing process for dicing the wafer to each chip.
    Type: Application
    Filed: July 1, 2004
    Publication date: November 25, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Shinsuke Nakajyo, Yoshiyuki Yoneda, Hideharu Sakoda
  • Patent number: 6777250
    Abstract: A method of manufacturing semiconductor device in the method of manufacturing wafer level semiconductor device that can search the defective products from the marking information even when sealing resin is formed on the wafer and a semiconductor device manufactured with the same method. A method of manufacturing wafer level semiconductor comprises a process to seal with a resin material the surface of wafer having the front surface and rear surface and forming a plurality of semiconductor chips on the front surface, a first marking process for marking the position information corresponding to each chip to the region of each chip at the rear surface of the wafer, a process for performing the electrical test to each chip, a second marking process for marking the result of the electrical test to the region of each chip at the rear surface of the wafer and a dicing process for dicing the wafer to each chip.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: August 17, 2004
    Assignee: Fujitsu Limited
    Inventors: Shinsuke Nakajyo, Yoshiyuki Yoneda, Hideharu Sakoda
  • Patent number: 6600217
    Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: July 29, 2003
    Assignee: Fujitsu Limited
    Inventors: Masanori Onodera, Shinsuke Nakajyo, Masamitsu Ikumo
  • Patent number: 6420213
    Abstract: A number of processes and the cost for mounting the semiconductor device are reduced by reducing the number of kinds of adhesives necessary for mounting the semiconductor device having a plurality of stud bumps to a mounting substrate. An electrically non-conductive adhesive is applied to a planer surface of a hard material member. The semiconductor device is attached to a bonding head. The stud bumps of the semiconductor device are leveled by being pressed against the planer surface of the hard material member by the bonding head. A predetermined amount of the electrically non-conductive adhesive can be applied to a mounting area of the semiconductor device by separating the semiconductor device from the planer surface of the hard material member. The semiconductor device is fixed to the mounting substrate by placing the semiconductor device on the mounting substrate and curing the electrically non-conductive adhesive on the mounting surface of the semiconductor device.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: July 16, 2002
    Assignee: Fujitsu Limited
    Inventors: Shinsuke Nakajyo, Masanori Onodera, Masamitsu Ikumo
  • Publication number: 20010013641
    Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.
    Type: Application
    Filed: December 8, 2000
    Publication date: August 16, 2001
    Inventors: Masanori Onodera, Shinsuke Nakajyo, Masamitsu Ikumo