Patents by Inventor Shintaro Arai
Shintaro Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230010658Abstract: The present invention relates to an electronic switching device comprising an organic molecular layer in contact with a metal nitride electrode for use in memory, sensors, field-effect transistors or Josephson junctions. More particularly, the invention is included in the field of random access non-volatile memristive memories (RRAM). The invention thus further relates to an electronic component comprising a crossbar array comprising a multitude of said electronic switching devices.Type: ApplicationFiled: October 20, 2020Publication date: January 12, 2023Applicant: Merck Patent GmbHInventors: Peer KIRSCH, Sebastian RESCH, Henning SEIM, Itai LIEBERMAN, Shintaro ARAI, Marc TORNOW, Takuya KAMIYAMA, Julian DLUGOSCH, Mansour MOINPOUR
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Publication number: 20160308013Abstract: A semiconductor device production method includes preparing a first structure having a first planar semiconductor layer, and a first columnar semiconductor layer on the first planar semiconductor layer. A first high concentration semiconductor layer is formed in a lower region of the first columnar semiconductor layer and in a region of the first planar semiconductor layer below the first columnar semiconductor layer. An insulating layer, a metal film, and a semiconductor film are sequentially formed on the first structure, and the semiconductor film, the metal film, and the insulating layer are sequentially etched with each leaving a sidewall shape on the sidewall on the first columnar semiconductor layer following etching. Another semiconductor film is then formed on the sidewall shape after etching the insulating film.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Publication number: 20150357428Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Patent number: 9153697Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: GrantFiled: May 26, 2011Date of Patent: October 6, 2015Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8755219Abstract: In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area.Type: GrantFiled: February 8, 2013Date of Patent: June 17, 2014Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Patent number: 8754481Abstract: An SGT-based static memory cell which is a six-transistor SRAM cell includes an SGT driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an SGT selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an SGT load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor. A voltage applied to the second gate electrode is lower than a voltage applied to a first-conductivity-type high-concentration semiconductor layer on the upper part of the island-shaped semiconductor layer of the selection transistor.Type: GrantFiled: October 18, 2012Date of Patent: June 17, 2014Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai
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Patent number: 8647947Abstract: It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.Type: GrantFiled: June 13, 2013Date of Patent: February 11, 2014Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Publication number: 20140016403Abstract: In a loadless 4T-SRAM constituted using vertical-type transistor SGTs, a small SRAM cell area is realized. In a static memory cell constituted using four MOS transistors, the MOS transistors are SGTs formed on a bulk substrate in which the drains, gates, and sources are arranged in the vertical direction. The gates of access transistors are shared, as a word line, among a plurality of cells adjacent to one another in the horizontal direction. One contact for the word line is formed for each group of cells, thereby realizing a CMOS-type loadless 4T-SRAM with a very small memory cell area.Type: ApplicationFiled: February 8, 2013Publication date: January 16, 2014Inventors: FUJIO MASUOKA, SHINTARO ARAI
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Patent number: 8609494Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 16, 2013Date of Patent: December 17, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8598650Abstract: It is intended to provide a semiconductor device comprising a circuit which has a connection between a drain region or a source region of a first MOS transistor and a drain region or a source region of a second MOS transistor. Each surround gate transistor (SGT) has a gate electrode that surrounds a sidewall of a pillar-shaped semiconductor layer.Type: GrantFiled: February 12, 2010Date of Patent: December 3, 2013Assignee: Unisantis Electronics Singapore PTE Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Patent number: 8563379Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: GrantFiled: December 10, 2012Date of Patent: October 22, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130273703Abstract: It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.Type: ApplicationFiled: June 13, 2013Publication date: October 17, 2013Inventors: Fujio MASUOKA, Shintaro ARAI
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Publication number: 20130252413Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: Unisantis Eletronics Singapore Pte.Ltd.Inventors: Fujio MASUOKA, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130228869Abstract: An SGT-based static memory cell which is a six-transistor SRAM cell includes an SGT driver transistor including a first gate electrode surrounding a first gate insulating film and composed of at least a metal; an SGT selection transistor including a second gate electrode surrounding a second gate insulating film and composed of at least a metal; an SGT load transistor including a third gate electrode surrounding a third gate insulating film and composed of at least a metal; and a gate wire connected to the second gate electrode. An island-shaped semiconductor layer of the driver transistor has a peripheral length that is less than twice that of an island-shaped semiconductor layer of the selection transistor. A voltage applied to the second gate electrode is lower than a voltage applied to a first-conductivity-type high-concentration semiconductor layer on the upper part of the island-shaped semiconductor layer of the selection transistor.Type: ApplicationFiled: October 18, 2012Publication date: September 5, 2013Applicant: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: FUJIO MASUOKA, HIROKI NAKAMURA, SHINTARO ARAI
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Patent number: 8519475Abstract: A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.Type: GrantFiled: November 4, 2011Date of Patent: August 27, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Navab Singh, Kavitha Devi Buddharaju, Shen Nansheng, Rukmani Devi Sayanthan
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Patent number: 8507995Abstract: In a static memory cell configured using four MOS transistors and two load resistance elements, the MOS transistors are formed on diffusion layers formed on a substrate. The diffusion layers serve as memory nodes. The drain, gate and source of the MOS transistors are arranged in the direction orthogonal to the substrate, and the gate surrounds a columnar semiconductor layer. In addition, the load resistance elements are formed by contact plugs. In this way, it is possible to form a SRAM cell with a small area.Type: GrantFiled: September 15, 2010Date of Patent: August 13, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Patent number: 8497548Abstract: It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar.Type: GrantFiled: April 27, 2010Date of Patent: July 30, 2013Assignee: Unisantis Electronics Singapore PTE Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Patent number: 8486785Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 23, 2011Date of Patent: July 16, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8476132Abstract: It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillarType: GrantFiled: February 11, 2010Date of Patent: July 2, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai
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Patent number: 8466512Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: GrantFiled: August 18, 2010Date of Patent: June 18, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh