Abstract: Disclosed herein is a method of generating an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which a high-level synthesis unit generates a control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.

Abstract: Generate an RTL description that implements any functional safety system. A high-level synthesis method for generating an RTL description in which a functional safety system is inserted by using an operation description defining a functional logic, a high-level synthesis script defining a high-level synthesis constraint, and a functional safety system implementation specification specifying a functional safety system to be inserted in a high-level synthesis process. The high-level synthesis method includes a control data flow graph generation step in which the high-level synthesis unit generates the control data flow graph using the operation description, and a first function safety system insertion processing step in which the high-level synthesis unit inserts the function safety system into the control data flow graph according to the function safety system implementation specification after the control data flow graph generation step.

Abstract: Specific characteristics of a branch structure between a behavioral description and a hardware description, a structural dependence relation therebetween, and the like are extracted and used to shorten the time of processing for equivalence checking, thereby contributing to the shortening of a processing time required for equivalence checking for a high-level description and a behavioral synthesis result. Upon checking of the equivalence of a high-level description and a synthesis result obtained by performing a behavior synthesis on the high-level description according to a behavioral synthesis restriction, correspondence information between flip-flops with a feedback loop in the synthesis result and variables associated therewith with a backward data dependence relation in a high-level description is generated and used.