Patents by Inventor Shintaro Kaido

Shintaro Kaido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8901016
    Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 2, 2014
    Assignee: ASM Japan K.K.
    Inventors: Jeongseok Ha, Hideaki Fukuda, Shintaro Kaido
  • Publication number: 20120164846
    Abstract: A method of forming a metal oxide hardmask on a template includes: providing a template constituted by a photoresist or amorphous carbon formed on a substrate; and depositing by atomic layer deposition (ALD) a metal oxide hardmask on the template constituted by a material having a formula SixM(1-x)Oy wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Applicant: ASM JAPAN K.K.
    Inventors: Jeongseok Ha, Hideaki Fukuda, Shintaro Kaido
  • Publication number: 20070065597
    Abstract: A plasma CVD apparatus for forming a thin film on a wafer having diameter Dw and thickness Tw, includes: a vacuum chamber; a shower plate; a top plate; a top mask portion for covering a top surface peripheral portion of the wafer; and a side mask portion for covering a side surface portion of the wafer. The side mask portion has an inner diameter of Dw+?, and the top mask portion is disposed at a clearance of Tw+? between a bottom surface of the top mask portion and a wafer-supporting surface of the top plate, wherein ? is more than zero, and ? is more than zero.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 22, 2007
    Applicants: ASM JAPAN K.K., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shintaro Kaido, Masashi Yamaguchi, Yoshinori Morisada, Nobuo Matsuki, Kyu Na, Eun Baek