Abstract: An arithmetic circuit is provided in which the circuit scale can be reduced and the circuit delay can be shortened. The upper 24 bits and lower 16 bits of the 40 bit data A and B, that is input into the arithmetic circuit 100, are calculated in the first arithmetic circuit 110 and the second arithmetic circuit 120, respectively. The carry transmission control circuit 130 transmits the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the arithmetic circuit dividing signal p does not divide the arithmetic circuit, and the command control circuit 140 outputs an identical command to each of the arithmetic circuits. As a result, this circuit becomes an arithmetic circuit of 40 bits. The carry transmission control circuit 130 stops the transmission of the carry between the arithmetic circuit 120 and the arithmetic circuit 110 when the signal p divides the arithmetic circuit, and the command control circuit 140 outputs each of the independent commands to each of the arithmetic circuits.