Patents by Inventor Shintaro Mori

Shintaro Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8941421
    Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeki Nakamura, Shintaro Mori, Yoshinori Tokioka, Kenji Tokami
  • Patent number: 8721495
    Abstract: A motorized rear derailleur is basically provided with a base member, a movable member, a pulley arrangement, a motor unit and a power limit circuit. The movable member is movably mounted to the base member between a plurality of gear positions. The pulley arrangement is supported by the movable member. The pulley arrangement includes a pulley having a dynamo that generates electrical energy in response to rotation of the pulley. The motor unit is operatively coupled between the base member and the movable member to selectively move the movable member relative to the base member between the gear positions. The motor unit is electrically coupled to the dynamo to selectively receive electrical energy generated by the dynamo. The power limit circuit is electrically coupled between the dynamo and the motor unit.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: May 13, 2014
    Assignee: Shimano Inc.
    Inventors: Satoshi Kitamura, Shintaro Mori
  • Publication number: 20140084972
    Abstract: To provide a semiconductor device provided with a power-on reset circuit that can reliably detect decrease in power-supply voltage. The power-on reset circuit provided on the semiconductor device includes: a first comparison circuit that compares a primary voltage with a reference value; and a second comparison circuit that compares a secondary voltage with the reference value. The power-on reset circuit issues a reset signal based on comparison results of the first and second comparison circuits.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki NAKAMURA, Shintaro MORI, Yoshinori TOKIOKA, Kenji TOKAMI
  • Publication number: 20140084983
    Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 27, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshinori Tokioka, Kenji Tokami, Shintaro Mori, Shigeki Nakamura
  • Publication number: 20130145885
    Abstract: A bicycle generator or a shifting device has a base member, a rotation receiving member and a dynamo. The base member is configured to be mounted only in vicinity of a hub axle. The rotation receiving member is rotatably mounted on the base member and is rotated by a rotational part of a bicycle. The dynamo is coupled to the rotation receiving member to generate electrical energy in response to rotation of the rotation receiving member. In the case of the shifting device, a shifting unit is provided that includes an electric motor and an output member that engages a part of a bicycle hub transmission device.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: SHIMANO INC.
    Inventors: Satoshi KITAMURA, Shintaro MORI
  • Patent number: 8402664
    Abstract: An electric control device is provided with a fixed member, a user operating member and a position sensing unit. The fixed member has a bicycle mounting part. The user operating member is movably mounted to the fixed member. The user operating member includes a first magnetic element. The position sensing unit has a rotating member and a position sensor. The position sensor senses a position of the rotating member. The rotating member includes a second magnetic element that rotates the rotating member as the user operating member is moved. At least one of the first and second magnetic elements is configured to generate a magnetic field.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 26, 2013
    Assignee: Shimano Inc.
    Inventors: Satoshi Kitamura, Shintaro Mori
  • Publication number: 20120322594
    Abstract: A bicycle chain tensioner device is basically provided with a base member, a pulley and an electrical storage unit. The pulley is supported by the base member. The pulley includes a dynamo that generates electrical energy in response to the pulley being rotated by a bicycle chain. The electrical storage unit is disposed on the base member and electrically coupled to the dynamo to store electrical energy generated by the dynamo.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: SHIMANO INC.
    Inventors: Satoshi KITAMURA, Shintaro MORI
  • Publication number: 20120322591
    Abstract: A motorized rear derailleur is basically provided with a base member, a movable member, a pulley arrangement, a motor unit and a power limit circuit. The movable member is movably mounted to the base member between a plurality of gear positions. The pulley arrangement is supported by the movable member. The pulley arrangement includes a pulley having a dynamo that generates electrical energy in response to rotation of the pulley. The motor unit is operatively coupled between the base member and the movable member to selectively move the movable member relative to the base member between the gear positions. The motor unit is electrically coupled to the dynamo to selectively receive electrical energy generated by the dynamo. The power limit circuit is electrically coupled between the dynamo and the motor unit.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: SHIMANO INC.
    Inventors: Satoshi KITAMURA, Shintaro MORI
  • Patent number: 8163105
    Abstract: The present invention provides a corrosion inhibition method which minimizes environmental adverse effects by using phosphate base anticorrosives without using zinc salt base anticorrosives and by reducing the concentration of the phosphate base anticorrosives, enables stable formation of an effective initial protective film, and does not affect water treatment after the formation of the initial protective film. In an initial protective film formation process of forming an initial protective film on a surface of an iron-based metallic member of a water system by adding anticorrosives to the water system, at least one selected from a group consisting of pyrophosphoric acids and pyrophosphates is employed as the anticorrosives and the initial protective film formation process is conducted such that the initial pH at the start of the initial protective film formation process is adjusted to be 5 or more and less than 7 so that the pH at the end of the initial protective film formation process becomes 7 or more.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: April 24, 2012
    Assignee: Kurita Water Industries Ltd.
    Inventors: Yutaka Yoneda, Hajime Iseri, Shintaro Mori
  • Publication number: 20070197177
    Abstract: The present invention provides a squelch detecting circuit capable of high-speed transfer while using a reduced number of high-speed operating operational amplifiers to reduce power consumption and the cost of parts. Input differential signals inputted to a differential amplification circuit are amplified and the amplified signal is outputted to a gain proportion circuit. The gain proportion circuit supplies a potential holding circuit with a potential proportional to the amplified signal. The potential holding circuit holds the potential supplied from the gain proportion circuit. A comparator circuit compares the potential held by the potential holding circuit with a reference potential to decide whether it is a squelch state or a non-squelch state and outputs the result as a detect signal.
    Type: Application
    Filed: April 16, 2007
    Publication date: August 23, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Danichi Komatsu, Shintaro Mori
  • Patent number: 7218903
    Abstract: The present invention provides a squelch detecting circuit capable of high-speed transfer while using a reduced number of high-speed operating operational amplifiers to reduce power consumption and the cost of parts. Input differential signals inputted to a differential amplification circuit are amplified and the amplified signal is outputted to a gain proportion circuit. The gain proportion circuit supplies a potential holding circuit with a potential proportional to the amplified signal. The potential holding circuit holds the potential supplied from the gain proportion circuit. A comparator circuit compares the potential held by the potential holding circuit with a reference potential to decide whether it is a squelch state or a non-squelch state and outputs the result as a detect signal.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: May 15, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Danichi Komatsu, Shintaro Mori
  • Patent number: 7148567
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a–40e, 41a–41e and 42a–42d), a plurality of LEADs (50a–50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a–60e and 61a–61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a–40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a–50d).
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: December 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Publication number: 20050221013
    Abstract: The present invention provides a corrosion inhibition method which minimizes environmental adverse effects by using phosphate base anticorrosives without using zinc salt base anticorrosives and by reducing the concentration of the phosphate base anticorrosives, enables stable formation of an effective initial protective film, and does not affect water treatment after the formation of the initial protective film. In an initial protective film formation process of forming an initial protective film on a surface of an iron-based metallic member of a water system by adding anticorrosives to the water system, at least one selected from a group consisting of pyrophosphoric acids and pyrophosphates is employed as the anticorrosives and the initial protective film formation process is conducted such that the initial pH at the start of the initial protective film formation process is adjusted to be 5 or more and less than 7 so that the pH at the end of the initial protective film formation process becomes 7 or more.
    Type: Application
    Filed: March 22, 2005
    Publication date: October 6, 2005
    Applicant: KURITA WATER INDUSTRIES LTD
    Inventors: Yutaka Yoneda, Hajime Iseri, Shintaro Mori
  • Publication number: 20050156305
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a-40e, 41a-41e and 42a-42d), a plurality of LEADs (50a-50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a-60e and 61a-61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a-40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a-50d).
    Type: Application
    Filed: March 14, 2005
    Publication date: July 21, 2005
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Publication number: 20050054311
    Abstract: The present invention provides a squelch detecting circuit capable of high-speed transfer while using a reduced number of high-speed operating operational amplifiers to reduce power consumption and the cost of parts. Input differential signals inputted to a differential amplification circuit are amplified and the amplified signal is outputted to a gain proportion circuit. The gain proportion circuit supplies a potential holding circuit with a potential proportional to the amplified signal. The potential holding circuit holds the potential supplied from the gain proportion circuit. A comparator circuit compares the potential held by the potential holding circuit with a reference potential to decide whether it is a squelch state or a non-squelch state and outputs the result as a detect signal.
    Type: Application
    Filed: September 8, 2004
    Publication date: March 10, 2005
    Inventors: Danichi Komatsu, Shintaro Mori
  • Patent number: 6807647
    Abstract: An IC test system comprises: a test pattern signal applying section for applying a test pattern signal to an IC to be tested, in accordance with a test program; a simulation section for simulating an operation of the test pattern signal applying section in accordance with a simulation program; and a management device which is connected detachably with the test pattern signal applying section, for managing the operation of the test pattern signal applying section and an operation of the simulation section in accordance with a management program, for storing information about each operation of the test pattern signal applying section and the simulation section, and for managing one of the information about the operation of the simulation section and the information about the operation of the test pattern signal applying section in accordance with the other information.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: October 19, 2004
    Assignee: Ando Electric Co., Ltd.
    Inventor: Shintaro Mori
  • Patent number: 6674623
    Abstract: In a microcomputer equipped with a built-in temperature sensor, diodes as a temperature sensor are incorporated in a pair of circuit blocks, respectively, and placed in opposite polarity connection to each other. When detecting a temperature of the microcomputer, a constant current If is supplied to the diodes through terminals commonly connected to both the diodes. A voltage Vf generated at each diode is read through terminals located at more adjacent nodes to the diode when compared in position with the terminals.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: January 6, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshihiro Abe, Shintaro Mori, Fumihiko Terayama, Masahiro Kitamura, Seiichi Yamazaki, Yasuo Moriguchi
  • Publication number: 20030102556
    Abstract: A semiconductor integrated circuit device has two semiconductor integrated circuit chips (20 and 30) respectively provided with a plurality of PADs (40a-40e, 41a-41e and 42a-42d), a plurality of LEADs (50a-50d) disposed around arrays of the semiconductor integrated circuit chips, and a plurality of bonding wires (60a-60e and 61a-61d). The plurality of bonding wires are connected so as not to straddle one semiconductor integrated circuit chip (30) and allow wiring between the PADs (40a-40e) of the other semiconductor integrated circuit chip (20) and the LEADs (50a-50d).
    Type: Application
    Filed: June 4, 2002
    Publication date: June 5, 2003
    Inventors: Yasuo Moriguchi, Shintaro Mori, Fumihiko Terayama, Hirokazu Komoriya
  • Publication number: 20020049945
    Abstract: An IC test system comprises: a test pattern signal applying section for applying a test pattern signal to an IC to be tested, in accordance with a test program; a simulation section for simulating an operation of the test pattern signal applying section in accordance with a simulation program; and a management device which is connected detachably with the test pattern signal applying section, for managing the operation of the test pattern signal applying section and an operation of the simulation section in accordance with a management program, for storing information about each operation of the test pattern signal applying section and the simulation section, and for managing one of the information about the operation of the simulation section and the information about the operation of the test pattern signal applying section in accordance with the other information.
    Type: Application
    Filed: September 5, 2001
    Publication date: April 25, 2002
    Applicant: ANDO ELECTRIC CO., LTD
    Inventor: Shintaro Mori
  • Patent number: 4985648
    Abstract: Respective current supply means (I.sub.A, I.sub.B) control conducting periods of corresponding transistors (Q.sub.3, Q.sub.4), whereby conducting periods of driving transistore (Q.sub.6, Q.sub.7) are also controlled. Thus, periods in which both of the driving transistors (Q.sub.6, Q.sub.7) simultaneously enter ON states are reduced and through current (I.sub.S) flowing to the ground level GND through the driving transistors (Q.sub.6, Q.sub.7) is reduced. A pull-down transistor (Q.sub.8) controls a conducting period of the driving transistor (Q.sub.7), whereby periods in which both of the driving transistors (Q.sub.6, Q.sub.7) simultaneously enter ON states are reduced and the through current (I.sub.S) is reduced.
    Type: Grant
    Filed: July 18, 1989
    Date of Patent: January 15, 1991
    Assignees: Matsushita Electric Industrial Co. Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiaki Tsuruoka, Masafumi Nakamura, Shintaro Mori