Abstract: There is provided an analyzing apparatus for finding the possibility of dividing up and executing a source program using debugging information generated when compiling the source program and memory access information generated by running object code on a simulator. The analyzing apparatus includes: a memory that stores block IDs for grouping some out of the source statements in the source program as processing blocks associated with code memory addresses of respective instructions, based on the debugging information; and a graphical display functional unit that graphically displays, on a display device, based on the memory access information and together with cycle times, an access state for execution memory when the source program is performed, the access state including code memory addresses, variable memory addresses, and access types and being displayed using a different style for each block ID associated with the code memory addresses of the respective instructions.

Abstract: A data processing system includes the data processing apparatuses formed with the VUPU architecture by combining a general-purpose data processing unit and a special-purpose data processing unit equipped with a data path unit for specialized data processing that is executed according to special-purpose instructions, and equipping the general-purpose data processing unit with a communication function for communicating with the general-purpose data processing unit in another data processing apparatus. In this invention, these data processing apparatuses are combined to form the system with plurality of specialized circuits, therefore, the data processing system in which parallel processing is performed by a plurality of specialized circuits can be provided economically and in a short time.

Abstract: A data processing system that simulates operation of a processor for an application program including instruction sets is provided by this invention. To solve the problem that an instruction cycle of each of the instruction sets is performed with plurality of pipeline stages in the processor, the data processing system comprises cycle-level simulating means for simulating operation of the processor controlled by the application program in cycles of the pipeline stages. By the cycle-level or based simulation of hardware using a high-speed simulator written in a high-level language such as C language, it becomes possible to provide a simulator that maintains the same level (cycle basis) of accuracy as a conventional RTL-based simulator but that operates with between several hundred and several thousand times the simulation speed.

Abstract: A data processing system includes the data processing apparatuses formed with the VUPU architecture by combining a general-purpose data processing unit and a special-purpose data processing unit equipped with a data path unit for specialized data processing that is executed according to special-purpose instructions, and equipping the general-purpose data processing unit with a communication function for communicating with the general-purpose data processing unit in another data processing apparatus. In this invention, these data processing apparatuses are combined to form the system with plurality of specialized circuits, therefore, the data processing system in which parallel processing is performed by a plurality of specialized circuits can be provided economically and in a short time.

Abstract: A data processing system is provided that includes a special purpose data processing unit (VU) specialized in a specific data processing according to a special purpose instruction, and a general purpose data processing unit (PU) capable of designating processes by general purpose instructions, and an instruction issue unit for supplying signals corresponding to the special purpose instruction and the general purpose instructions to the PU and the VU respectively, the instruction issue unit being an application-specific unit. By replacing the instruction issue unit with a sequencer specialized in the application, a reliable, compact, low-power consumption data processing system is provided in a short period using the resources resulting from optimization with the programmable VUPU processor capable of flexibly dealing with the specification change while maintaining the real-time response.

Abstract: All nodes in a network are classified into hierarchical groups. Each node belongs to any group in all hierarchical groups from the highest order group to the lowest order group. The node is assigned a hierarchical address corresponding to each hierarchical group. Thus, the amount of routing information required for data transfer can be reduced, thereby efficiently transmitting data.

Abstract: A variable logic operation apparatus which receives n-nary input data, logic function setting data and connection data, and performs logic operations on the input data based on a logic expression. The apparatus includes a plurality of logic operation units, each logic operation unit selecting a respective logic operation from a group of at least one logic operation, and outputting a single result based on the selected logic operation. The selected logic operation is selected by the logic function setting data. A plurality of connection devices connect the plurality of logic operation units in accordance with the connection data to form a tree structure. The tree structure is changeable by changing the connection data. Thus, the logic expression is converted into the tree structure in accordance with the setting data and the connection data.