Patents by Inventor Shintaro Suzumura
Shintaro Suzumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150222227Abstract: A monitoring system includes a slave device (4) and a master device (5). The slave device (4) superposes a current signal, which represents measurement data obtained by measuring each of one or more solar cell panels included in plural solar cell panels (P1 to P15) constituting a solar cell string (10), to a DC current path. The DC current path includes plural power lines (L1 to L14), a first trunk power line (21), and a second trunk power line (22). The master device (5) is connected onto the first trunk power line (21), second trunk power line (22), or both of the trunk power lines, and receives the measurement data from the slave device (4). Accordingly, the communication performance between the slave device and master device in, for example, a monitoring system that performs monitoring in units of a solar cell panel can be improved.Type: ApplicationFiled: February 4, 2014Publication date: August 6, 2015Applicant: Hitachi Industry & Control Solutions, Ltd.Inventors: Sadao Nishizawa, Shintaro Suzumura, Tetsuo Itou, Hideki Yoshida, Yuji Kasai, Masahiro Murakawa
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Patent number: 6980385Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.Type: GrantFiled: August 10, 2004Date of Patent: December 27, 2005Assignees: Hitachi Video and Information System, Inc., Hitachi Global Storage Technologies Japan, Ltd.Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
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Publication number: 20050041316Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.Type: ApplicationFiled: August 10, 2004Publication date: February 24, 2005Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
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Patent number: 6791776Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.Type: GrantFiled: February 28, 2001Date of Patent: September 14, 2004Assignees: Hitachi, Ltd., Hitachi Video and Information System, Inc.Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
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Patent number: 6700721Abstract: A magnetic recording and reproducing apparatus includes a R/W signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the R/W amplifier via a plurality of signal lines. In addition, the R/W amplifier has a compound circuit provided for the write data of the interleave system from the R/W signal processor and is formed as an integrated circuit, moreover, a ½ prescaler is provided at the output of the write data generator, making transmitting and receiving write data in NRZI CODE.Type: GrantFiled: July 10, 2002Date of Patent: March 2, 2004Assignee: Hitachi, Ltd.Inventors: Eisaku Saiki, Shintaro Suzumura, Terumi Takashi, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Shoichi Miyazawa, Masashi Mori
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Publication number: 20020171960Abstract: A magnetic recording and reproducing apparatus includes a R/W signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the R/W amplifier via a plurality of signal lines. In addition, the R/W amplifier has a compound circuit provided for the write data of the interleave system from the R/W signal processor and is formed as an integrated circuit, moreover, a ½ prescaler is provided at the output of the write data generator, making transmitting and receiving write data in NRZI CODE.Type: ApplicationFiled: July 10, 2002Publication date: November 21, 2002Inventors: Eisaku Saiki, Shintaro Suzumura, Terumi Takashi, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Shoichi Miyazawa, Masashi Mori
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Patent number: 6452736Abstract: A magnetic recording and reproducing apparatus includes a read/write signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the read/write amplifier via a plurality of signal lines. In addition, the read/write amplifier has a compound circuit provided for the write data of the interleave system from the read/write signal processor and is formed as an integrated circuit, moreover, a 1/2 prescaler is provided at the output of the write data generator, transmitting and receiving write data in Non-Return-To-Zero-Interleave CODE.Type: GrantFiled: May 25, 1995Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Eisaku Saiki, Shintaro Suzumura, Terumi Takashi, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Shoichi Miyazawa, Masashi Mori
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Publication number: 20010043416Abstract: In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.Type: ApplicationFiled: February 28, 2001Publication date: November 22, 2001Inventors: Takatoshi Kato, Takushi Nishiya, Hideyuki Yamakawa, Takashi Nara, Nobuaki Nakai, Hiroshi Ide, Shintaro Suzumura, Terumi Takashi
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Patent number: 5937020Abstract: Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.Type: GrantFiled: September 25, 1996Date of Patent: August 10, 1999Assignee: Hitachi, Ltd.Inventors: Kenichi Hase, Ryutaro Horita, Tsuguyoshi Hirooka, Haruto Katsu, Takashi Nara, Shoichi Miyazawa, deceased, Shintaro Suzumura
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Patent number: 5872666Abstract: Reproducing apparatus with an A/D (analog-to-digital) converter, which realizes high-accuracy data sampling, high-speed data transfer, low dissipation power and low cost. PR (partial response) processing is performed by receiving encoded signals, delaying the received signals on the basis of a reference clock, and adding the delayed signals and the received signals in analog signal form. The added signals are converted into digital values on the basis of the reference clock by the A/D converter, and Viterbi decoding is performed on the basis of the converted digital values. Owing to the PR processing which is performed at a stage preceding the A/D converter, a frequency band for the A/D conversion can be lowered, and hence, the high-accuracy data sampling is permitted.Type: GrantFiled: November 17, 1995Date of Patent: February 16, 1999Assignee: Hitachi, Ltd.Inventors: Eisaku Saiki, Kazutosi Ashikawa, Seiichi Mita, Shintaro Suzumura, Shoichi Miyazawa, Tsuguyoshi Hirooka
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Patent number: 5867333Abstract: A magnetic recording and reproducing apparatus such as a disk drive has a phase locked loop circuit which is less susceptible to an effect of noise of a power supply and ground and reduces a clock jitter. The magnetic recording and reproducing apparatus is compatible to a constant density recording system without increasing a circuit scale and a power consumption and with a small number of IC pins. The phase locked loop circuit of the magnetic recording and reproducing apparatus is provided with two D/A converter circuits to drive a loop filter. It is also provided with a circuit for distributing a reference potential of a voltage controlled oscillator (VCO) and a center frequency of the VCO, a gain of the VCO and a current gain of the D/A converter circuit are changed in linked relation. A reference voltage source is provided such that a center point or one end of the loop filter is connected to the reference voltage eliminating the ground connection.Type: GrantFiled: August 10, 1995Date of Patent: February 2, 1999Assignee: Hitachi, Ltd.Inventors: Eisaku Saiki, Shintaro Suzumura, Kazutoshi Ashikawa, Tsuguyoshi Hirooka, Seiichi Mita
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Phase locked loop circuit with adjustable offset characteristic, method for adjustment and apparatus
Patent number: 5677802Abstract: A phase locked loop circuit having a voltage controlled oscillator for generating a clock signal with a frequency determined by a voltage control signal supplied to the voltage controlled oscillator, an AD-conversion circuit for sampling a target signal with a timing determined by the clock signal and for converting sampled values into digital data, a phase locked loop control circuit for generating control data with values representing values of the digital data, and a DA-conversion circuit having an adjustable conversion characteristic for converting the control data into an analog signal and for outputting the analog signal to the voltage controlled oscillator as the voltage control signal.Type: GrantFiled: March 17, 1995Date of Patent: October 14, 1997Assignee: Hitachi, Ltd.Inventors: Eisaku Saiki, Masashi Mori, Shintaro Suzumura, Shoichi Miyazawa, Terumi Takashi -
Patent number: 5157354Abstract: A phase locked loop IC comprising a voltage controlled oscillator which generates a clock signal in accordance with a control voltage, a first ECL input buffer which is an input buffer for a signal to be synchronized, a phase-lock capture circuit for producing a current determinative of the control voltage in accordance with the phase difference and the frequency difference between the signal to be synchronized and the clock signal, and a phase-lock follow-up circuit for producing a current determinative of the control voltage in accordance with the phase difference between the clock signal and the signal to be synchronized; wherein the supply voltage system of the first ECL input buffer is so disposed as to be isolated from any of the supply voltage systems of the voltage-controlled oscillator, the phase-lock capture circuit and the phase lock follow-up circuit, while the ground system of the first ECL input buffer is so disposed as to be insolated from any of the ground systems of the voltage-controlled oscType: GrantFiled: November 27, 1991Date of Patent: October 20, 1992Assignees: Hitachi, Ltd., Hitachi Video & Information System, Inc.Inventors: Eisaku Saiki, Shintaro Suzumura, Fukashi Ohi, Akira Uragami, Tsuyoshi Tateyama