Abstract: A display control apparatus includes: a first selector that, when line-of-sight information indicating a direction in which a line of sight of an occupant of a vehicle is directed is outputted, selects one of a plurality of display apparatuses as a display apparatus for displaying information provided to the occupant of the vehicle, the plurality of display apparatuses being configured to display the information, the one display apparatus existing in the direction in which the line of sight is directed; and a second selector that, when the line-of-sight information is not outputted, selects, as the display apparatus for displaying the information, one of the plurality of display apparatuses to which the line of sight of the occupant is more likely to be directed than to other display apparatuses.

Abstract: An information processing apparatus is provided. This information processing apparatus includes a first OS that controls execution of a first application, a second OS that controls execution of a second application, and a hypervisor that is executed on a processor and controls execution of the first OS and the second OS.

Abstract: A software debugger tangibly embodied on a computer readable medium may display a microcomputer program being debugged so that a halt address at which the execution of the program is caused to halt can be distinguished from other addresses. When performing step-by-step execution of the program, a determination is made whether an instruction at the halt address is a predicate execution instruction or not. If the instruction is a predicate execution instruction, a condition flag value for the instruction is acquired. Based on the condition flag value, a determination is made whether the predicate execution instruction is to be executed or not. Then, the instruction at the halt address is displayed on a screen by changing a display method according to the result of the determination.

Abstract: Provided is a cache memory system which, in a system having a plurality of masters, effectively utilizes a bus band. The cache memory system comprises: a cache memory; a bus load judging device for performing judgment of a state of a bus that is connected to a recording device in which cache-target data of the cache memory is stored; and a replace-way controller for controlling a replacing form of the cache memory according to a result of judgment performed by the bus load judging device.

Abstract: In a software development support system for supporting the development of a program executable on a microcomputer having conditional instructions, it is an object of the invention to make provisions so that the executing process of the program's conditional logic structure implemented by a conditional instruction can be presented for viewing to the user in an easy-to-view form. To achieve this, a debugger is provided that has the functions of: when performing step-by-step execution of the program, determining whether an instruction at a halt address is a conditional instruction or not; if the instruction is a conditional instruction, then acquiring a condition flag value for the instruction; determining, based on the condition flag value, whether the conditional instruction is to be executed or not; and displaying the instruction at the halt address on a screen by changing display method according to the result of the determination.

Abstract: According to the signal processing method of the invention, control data is previously generated by using the name of a control signal included in an object signal, and then, the object signal including the control signal is input. The name of the control signal in the control data is substituted with the content of the control signal included in the object signal, and then the object signal is processed by a signal processing unit by using the control data including the content of the control signal. Therefore, the signal processing unit can change the processing to be performed on the object signal in accordance with the content of the control signal included in the object signal.

Abstract: A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.

Abstract: To achieve an LSI automated design satisfying a required function and a required performance with the reuse of existing design data, there are disposed: library element memory means for storing, in the form of elements, existing design data (circuit data) together with design procedures (conversion information) thereof; element arrangement entering means for entering an element arrangement for achieving the desired function; library element specializing means for determining the functions of general-purpose elements; element synthesizing means for synthesizing an element having one function in which the functions of the elements are combined with one another; design data memory means for storing a variety of data; conversion instruction entering means for entering a design target level; conversion method selecting means for selecting a method of converting the elements to the target level, based on information relating to the design procedure of each of the elements; and design data converting means for execu

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Abstract: With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.