Patents by Inventor Shintaro Wada
Shintaro Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122565Abstract: A user is presented with determination information obtained by determining a condition of a target site and feature information indicating a feature related to a condition of a body of a subject, which are generated from the same image representing the target site of the subject. A determination system includes an acquirer that acquires a target image representing a target site of a body of a subject, a first generator that generates first determination information indicating a condition of the target site from the target image used to generate the first determination information, a second generator that generates feature information indicating a feature related to a condition of the body of the subject from the target image, and a display controller that causes a display apparatus to display the first determination information and the feature information.Type: ApplicationFiled: January 25, 2022Publication date: April 18, 2024Inventors: Kenichi WATANABE, Masayuki KYOMOTO, Masahiko HASHIDA, Shintaro HONDA, Naoya WADA
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Publication number: 20240119587Abstract: A prediction image is generated and output that represents a condition of a target region of a subject. A prediction system includes a prediction information acquirer that acquires (a) a subject image representing a target region of a subject at a first time, and (b) first prediction information regarding the target region at a second time when a predetermined period has elapsed from the first time; and a prediction image generation unit that generates a prediction image indicating a condition of the target region at the second time from the subject image based on the first prediction information and output the prediction image.Type: ApplicationFiled: January 19, 2022Publication date: April 11, 2024Inventors: Kenichi WATANABE, Masayuki KYOMOTO, Masahiko HASHIDA, Shintaro HONDA, Naoya WADA
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Publication number: 20240093849Abstract: To prevent point illumination and fix a light-guiding body. The present invention includes: a fixation portion having a first holding portion and a second holding portion; engagement portions that restrict frontward movement of the one end portion in the front-back direction; an elastic portion that generates elastic force upward in the up-down direction, and abuts on the one end portion to maintain engagement of the engagement portions; contact portions that bring the first holding portion and the one end portion into contact with each other on both sides in the left-right direction; an abutment portion that abuts on the one end portion to restrict backward movement of the one end portion in the front-back direction; and a restriction portion that abuts on the elastic portion to restrict downward movement of the elastic portion in the up-down direction.Type: ApplicationFiled: December 1, 2021Publication date: March 21, 2024Applicant: ICHIKOH INDUSTRIES, LTD.Inventors: Seito WADA, Shintaro ABE
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Patent number: 11309153Abstract: The contact switching device includes a first terminal, a first contact, a second terminal, and a base. The first contact is attached to the first terminal. The base includes a first attachment portion, a second attachment portion, and a groove portion. The first terminal is attached to the first attachment portion. The second terminal is attached to the second attachment portion. The groove portion is arranged between the first attachment portion and the second attachment portion. The groove portion has a shape in which the inside is larger than the entrance.Type: GrantFiled: January 16, 2019Date of Patent: April 19, 2022Assignee: OMRON CORPORATIONInventors: Jun Sasaki, Kazuhiro Tsutsui, Hiroyuki Harimochi, Shintaro Wada, Yuki Muto, Kazuhiro Ikemoto, Keisuke Kihara
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Publication number: 20210043404Abstract: The contact switching device includes a first terminal, a first contact, a second terminal, and a base. The first contact is attached to the first terminal. The base includes a first attachment portion, a second attachment portion, and a groove portion. The first terminal is attached to the first attachment portion. The second terminal is attached to the second attachment portion. The groove portion is arranged between the first attachment portion and the second attachment portion. The groove portion has a shape in which the inside is larger than the entrance.Type: ApplicationFiled: January 16, 2019Publication date: February 11, 2021Inventors: Jun SASAKI, Kazuhiro TSUTSUI, Hiroyuki HARIMOCHI, Shintaro WADA, Yuki MUTO, Kazuhiro IKEMOTO, Keisuke KIHARA
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Electronic apparatus including memory modules that can operate in either memory mode or storage mode
Patent number: 10073644Abstract: An electronic apparatus includes a processor, non-volatile memory devices having first modules running in memory mode and second modules running in storage mode, and a memory controller. In response to a request to load data stored in a third module running in storage mode, into a space that is mapped by the memory controller, the processor changes the mode of the third module to memory mode and the memory controller creates a mapping for the data stored in the third module. In response to a request to copy data loaded into a space that is mapped by the memory controller to a module running in storage mode, the processor changes the mode of a third module, which is storing a portion of the data and running in memory mode, to storage mode.Type: GrantFiled: March 1, 2017Date of Patent: September 11, 2018Assignee: Toshiba Memory CorporationInventor: Shintaro Wada -
ELECTRONIC APPARATUS INCLUDING MEMORY MODULES THAT CAN OPERATE IN EITHER MEMORY MODE OR STORAGE MODE
Publication number: 20170269863Abstract: An electronic apparatus includes a processor, non-volatile memory devices having first modules running in memory mode and second modules running in storage mode, and a memory controller. In response to a request to load data stored in a third module running in storage mode, into a space that is mapped by the memory controller, the processor changes the mode of the third module to memory mode and the memory controller creates a mapping for the data stored in the third module. In response to a request to copy data loaded into a space that is mapped by the memory controller to a module running in storage mode, the processor changes the mode of a third module, which is storing a portion of the data and running in memory mode, to storage mode.Type: ApplicationFiled: March 1, 2017Publication date: September 21, 2017Inventor: Shintaro WADA -
Publication number: 20160239412Abstract: A storage apparatus comprises a plurality of storage devices that form a storage volume, a data buffer, and a first control unit that controls the storage apparatus and the data buffer. Each storage device includes a nonvolatile memory that includes a plurality of erasable memory blocks, and a second control unit that controls the nonvolatile memory. The second control unit is configured to execute a garbage collection process. The first control unit is configured to save in the data buffer data received by the storage apparatus for storage in a particular storage device when the data are received during a time period in which the particular storage devices is executing a garbage collection process, and write the data that are saved in the data buffer into the particular one of the plurality of storage devices after the garbage collection process is completed.Type: ApplicationFiled: August 26, 2015Publication date: August 18, 2016Inventor: Shintaro WADA
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Patent number: 9401238Abstract: A coil terminal has a winding section comprising an end of coiled wire wound therearound. The winding section is bent relative to a remaining section of the coil terminal. The winding section has a proximal wire engagement portion and a distal wire engagement portion spaced away from each other in a longitudinal direction of the winding section, and an intermediate region disposed between the proximal wire engagement portion and the distal wire engagement portion. The wire end is extended in the intermediate region without being wound around the intermediate region.Type: GrantFiled: January 5, 2015Date of Patent: July 26, 2016Assignee: OMRON CorporationInventors: Yoshiaki Mimura, Hironori Sanada, Hideto Yamauchi, Akira Tsurusaki, Shintaro Wada
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Patent number: 9348628Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.Type: GrantFiled: March 18, 2013Date of Patent: May 24, 2016Assignee: Hitachi, Ltd.Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
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Publication number: 20150262743Abstract: A coil terminal has a winding section comprising an end of coiled wire wound therearound. The winding section is bent relative to a remaining section of the coil terminal. The winding section has a proximal wire engagement portion and a distal wire engagement portion spaced away from each other in a longitudinal direction of the winding section, and an intermediate region disposed between the proximal wire engagement portion and the distal wire engagement portion. The wire end is extended in the intermediate region without being wound around the intermediate region.Type: ApplicationFiled: January 5, 2015Publication date: September 17, 2015Inventors: Yoshiaki Mimura, Hironori Sanada, Hideto Yamauchi, Akira Tsurusaki, Shintaro Wada
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Patent number: 8898675Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.Type: GrantFiled: December 6, 2011Date of Patent: November 25, 2014Assignee: Hitachi, Ltd.Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
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Patent number: 8695007Abstract: A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T1, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.Type: GrantFiled: March 4, 2011Date of Patent: April 8, 2014Assignee: Hitachi, Ltd.Inventors: Shintaro Wada, Shuhei Matsumoto, Hironori Inoue, Kenichiro Yamato
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Patent number: 8423999Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.Type: GrantFiled: July 12, 2010Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Shuhei Matsumoto, Hironori Inoue, Shintaro Wada
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Publication number: 20120174114Abstract: The method of calculating the processor utilization for each of logical processors in a computer, including the steps of: dividing the computation interval in which the processor utilization by each logical processor is to be calculated into a single task mode (ST) execution interval and a multitask mode (MT) execution interval, appropriately calculating them based on the before-and-after relation between two times; and adding the MT execution interval multiplied by a predetermined MT mode processor resource assignment ratio to the ST mode execution interval to obtain the processor utilization for the calculation-targeted logical processor in the computation interval.Type: ApplicationFiled: December 6, 2011Publication date: July 5, 2012Inventors: SHUHEI MATSUMOTO, Hironori Inoue, Shintaro Wada
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Publication number: 20110225591Abstract: A hypervisor calculates the total number of processor cycles (the number of processor cycles of one or more physical processors) in a first length of time based on the sum of the operating frequencies of the respective physical processors and the first length of time for each first length of time (for example, a scheduling initialization cycle T1, which will be explained further below). The hypervisor calculates for each virtual computer the number of possessing cycles, which is a value obtained by the total number of processor cycles being distributed in proportion to the service ratios of multiple virtual computers. In virtual processor scheduling, the hypervisor runs a virtual processor inside a virtual computer on any physical processor based on the number of hold cycles of each virtual computer.Type: ApplicationFiled: March 4, 2011Publication date: September 15, 2011Inventors: SHINTARO WADA, Shuhei Matsumoto, Hironori Inoue, Kenichiro Yamato
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Publication number: 20110010713Abstract: In a computer system according to the background art, when a request to halt a virtual processor was detected, the virtual processor was blocked. In the blocking method, latency of virtual halt exit of the virtual processor was so long that a problem of performance was caused. A virtual machine monitor selects either of a busy wait method for making repeatedly examination until the virtual halt state exits while the virtual processor stays on the physical processor and a blocking method for stopping execution of the virtual processor and scheduling other virtual processors on the physical processor while yielding the operating physical processor and checking off scheduling of the virtual processor to the physical processor, based on a virtual processor halt duration predicted value of the virtual processor which is an average value of latest N virtual processor halt durations of the virtual processor.Type: ApplicationFiled: July 12, 2010Publication date: January 13, 2011Applicant: HITACHI, LTD.Inventors: Shuhei MATSUMOTO, Hironori INOUE, Shintaro WADA
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Patent number: 5266371Abstract: An adhesive dressing sheet is disclosed, comprising a polymer film having a high flexibility, an adhesive layer provided on one side of the polymer film, a peeling liner temporarily provided on the adhesive layer, and a flexible sheet on the other side of the polymer film, wherein a bending line is provided on the peeling liner in a direction almost at right angles to the peeling direction of the liner, and the flexible sheet has self supporting properties such that when the liner is peeled off up to the bending line and bent, the liner bending piece does not expand to an angle of 90.degree. or more.Type: GrantFiled: September 1, 1992Date of Patent: November 30, 1993Assignee: Nitto Denko CorporationInventors: Tetsuji Sugii, Shintaro Wada, Masayuki Konno
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Patent number: 4922911Abstract: An electrode is disclosed, comprising an electrically conductive substrate and a shrinkable layer laminated on the substrate, wherein a cut is provided on the electrode so as to form a connection terminal portion projecting outwards upon shrinkage of the shrinkable layer.Type: GrantFiled: April 5, 1989Date of Patent: May 8, 1990Assignee: Nitto Denko CorporationInventors: Shintaro Wada, Yoichi Nomura, Hisanori Takahashi, Masayuki Konno
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Patent number: 4679563Abstract: A biomedical electrode comprising a flexible electrode plate which conforms to the skin surface of a living body, and an electrically conductive adhesive layer which fixes the electrode plate on the skin surface and transmits an electric signal from the living body to said electrode plate, wherein a non-contact area to which said conductive adhesive layer is not substantially bonded is formed on the electrode plate and an electrically conductive tongue for connecting a terminal which takes said electric signal from the living body to a biomedical diagnostic apparatus is provided on the non-contact area by forming cut thereon.Type: GrantFiled: January 28, 1986Date of Patent: July 14, 1987Assignee: Nitto Electric Industrial Co., Ltd.Inventors: Shintaro Wada, Hisanori Takahashi, Yoichi Nomura