Patents by Inventor Shintaro Yamamichi

Shintaro Yamamichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10098179
    Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: October 9, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Hirokazu Honda, Masaki Watanabe, Junichi Arita, Norio Okada, Jun Ueno, Masashi Nishimoto, Michitaka Kimura, Tomohiro Nishiyama
  • Patent number: 9520375
    Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Toyohiro Aoki, Hiroyuki Mori, Yasumitsu K. Orii, Kazushige Toriyama, Shintaro Yamamichi
  • Publication number: 20160322319
    Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.
    Type: Application
    Filed: April 30, 2015
    Publication date: November 3, 2016
    Inventors: Toyohiro Aoki, Hiroyuki Mori, Yasumitsu K. Orii, Kazushige Toriyama, Shintaro Yamamichi
  • Patent number: 9362263
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shintaro Yamamichi, Kenta Ogawa
  • Patent number: 9362262
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Patent number: 9324663
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, a side surface arranged between the first main surface and the second main surface, and a magnetic storage device, a first magnetic shield overlaying on the first main surface, a second magnetic shield overlaying on the second main surface, and a third magnetic shield overlaying on the side surface. The first and second magnetic shields are mechanically connected via the third magnetic shield.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takahito Watanabe, Shintaro Yamamichi, Yoshitaka Ushiyama
  • Publication number: 20150333048
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 19, 2015
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Patent number: 9172028
    Abstract: A yield of semiconductor devices having a magnetic shield is enhanced. A magnetic shield member SIE has a first shield member SIE1 and a second shield member SIE2. The first shield member SIE1 has a first facing region FP1 facing a first surface of a semiconductor chip SC. The second shield member SIE2 has a second facing region FP2 facing a second surface of the semiconductor chip SC. A resin layer RL1 has a portion thereof making contact with the first shield member SIE1, and has another portion thereof making contact with the second shield member SIE2. Then, the first shield member SIE1 and the second shield member SIE2 are magnetically coupled via the resin layer RL1 or directly. The first shield member SIE1 and the second shield member SIE2 cover a magnetic memory cell MR in plan view.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: October 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takahito Watanabe, Shintaro Yamamichi
  • Patent number: 9165879
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers, to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Kenta Ogawa
  • Patent number: 9117814
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 25, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Publication number: 20150171066
    Abstract: This invention is to improve performance of a semiconductor integrated circuit device. A semiconductor device has a peripheral circuit chip and a logic chip mounted over a wiring substrate. The wiring substrate and the peripheral circuit chip are electrically connected, and the peripheral circuit chip and the logic chip are electrically connected. The peripheral circuit chip includes a first peripheral circuit, a power supply controller, a temperature sensor and a first RAM. The logic chip includes a CPU, a second peripheral circuit and a second RAM. The first peripheral circuit and the first RAM are manufactured based on a first process rule. The CPU, the second peripheral circuit and the second RAM are manufactured based on a second process rule finer than the first process rule.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 18, 2015
    Inventors: Shintaro YAMAMICHI, Atsushi NAKAMURA, Masayuki ITO, Naoto TAOKA, Kentaro MORI
  • Patent number: 8975150
    Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
  • Publication number: 20150053474
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Application
    Filed: November 4, 2014
    Publication date: February 26, 2015
    Applicant: NEC CORPORATION
    Inventors: Yoshiki NAKASHIMA, Shintaro YAMAMICHI, Katsumi KIKUCHI, Kentaro MORI, Hideya MURAI
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai
  • Publication number: 20140367863
    Abstract: A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 18, 2014
    Applicant: NEC CORPORATION
    Inventors: SHINTARO YAMAMICHI, KENTARO MORI, HIDEYA MURAI
  • Publication number: 20140361410
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 11, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Publication number: 20140361411
    Abstract: This invention can reduce heat that is generated in a first semiconductor chip and transfers, to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 11, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Kenta Ogawa
  • Publication number: 20140327064
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Publication number: 20140329476
    Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
    Type: Application
    Filed: April 22, 2014
    Publication date: November 6, 2014
    Applicants: RENESAS ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Shintaro YAMAMICHI, Hirokazu HONDA, Masaki WATANABE, Junichi ARITA, Norio OKADA, Jun UENO, Masashi NISHIMOTO, Michitaka KIMURA, Tomohiro NISHIYAMA
  • Patent number: 8872334
    Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Yoshiki Nakashima, Kentaro Mori