Abstract: In one aspect, an improved craps system may comprise at least one camera and a dealer station having at least one dealer station memory, at least one dealer station display device, and at least one dealer station processor in communication with the at least one camera. The at least one dealer station processor may be configured to receive the information from the camera regarding the throw of dice and determine, based upon the information, whether the throw complies with one or more requirements for a proper throw of dice.

Abstract: A cutting insert includes a rake face, a flank face, a cutting edge formed at a ridge where the rake face and the flank face intersect, a land provided on the rake face along the cutting edge, a breaker groove provided in the rake face inside of the land, and a curved surface formed between a groove surface of the breaker groove and the land. A radius of curvature of the curved surface is 0.5 mm or greater.

Abstract: A cutting insert includes a rake face, a flank face, a cutting edge formed at a ridge where the rake face and the flank face intersect, a land provided on the rake face along the cutting edge, a breaker groove provided in the rake face inside of the land, and a curved surface formed between a groove surface of the breaker groove and the land. A radius of curvature of the curved surface is 0.5 mm or greater.

Abstract: Disclosed is an image forming apparatus that makes it possible to suppress the scale enlargement of the electric circuit, so as to make the apparatus highly flexible. The apparatus forms an image based on image data acquired by applying a rendering operation to depiction commands and includes: a converting section to convert input data to the depiction commands; a first rendering section to apply the rendering operation to a first depiction command; a second rendering section to apply the rendering operation to a second depiction command; a reading section to read out first information from the storage section; a determining section to determine whether the first rendering section or the second rendering section should apply the rendering operation to each of the depiction commands; and a control, section to make either the first rendering section or the second rendering section apply the rendering operation to each of the depiction commands.

Abstract: An image forming system comprising: a controller, provided with a list creation means to create a display list by analyzing PDL data, a decompression means to decompress compressed image data, a drawing means to execute drawing based on the image data, and a print data creation means to create the print data based on the image data, for sending the print data to a printer; and a rasterization accelerator, provided with a second drawing means to execute drawing processing based on the display list, and a compression means to compress the image data drawn by the second drawing unit, for sending the image data to the controller, wherein the rasterization accelerator comprises a determination means for determining, based on the information of the display list, whether to execute or not the compression of the image data, and a compression method in case of executing the compression.

Abstract: Disclosed is an image forming apparatus that makes it possible to suppress the scale enlargement of the electric circuit, so as to make the apparatus highly flexible. The apparatus forms an image based on image data acquired by applying a rendering operation to depiction commands and includes: a converting section to convert input data to the depiction commands; a first rendering section to apply the rendering operation to a first depiction command; a second rendering section to apply the rendering operation to a second depiction command; a reading section to read out first information from the storage section; a determining section to determine whether the first rendering section or the second rendering section should apply the rendering operation to each of the depiction commands; and a control, section to make either the first rendering section or the second rendering section apply the rendering operation to each of the depiction commands.

Abstract: An image forming system comprising: a controller, provided with a list creation means to create a display list by analyzing PDL data decompression means to decompress compressed image data, a drawing means to execute drawing based on the image data, and a print data creation means to create the print data based on the image data for sending the print data to a printer; and a rasterization accelerator, provided with a second drawing means to execute drawing processing based on the display list, and a compression means to compress the image data drawn by the second drawing unit, for sending the image data to the controller, wherein the rasterization accelerator comprises determination means for determining, based on the information of the display list, whether to execute or not the compression of the image data, and a compression method in case of executing the compression.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.

Abstract: A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.

Abstract: A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.

Abstract: A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory.

Abstract: A semiconductor memory device is capable of simultaneously carrying out a first operation and a second operation. The semiconductor memory device includes first and second control circuits, a select control circuit, and a select circuit. The first control circuit controls the first operation according to a first address signal and outputs a read start signal when the reading of the data is started. The second control circuit controls the second operation according to a second address signal and outputs a sequence flag when the first and second addresses coincide with each other. The select control circuit generates a select control signal. The select control signal is asserted if the second operation is carried out. The first control circuit instructs the select circuit to select the sequence flag if the select control signal is asserted or the data if the select control signal is negated.

Abstract: A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

Abstract: A semiconductor memory device includes a semiconductor memory, an auto-operation control circuit which outputs a clock signal, a sync read control circuit which outputs a sync read address in sync with the clock signal, a read control circuit which selects a read address of the semiconductor memory in accordance with an address of the sync read address, a read sense amplifier circuit which outputs a data read signal that is produced by sensing data that is read out of the semiconductor memory in accordance with the read address, and a determination circuit which compares the data read signal with an expectation value.

Abstract: A throw-away insert for low-depth-of-cut finish cutting can be used over a wide range of feed rates. A breaker groove is provided between the center land and each cutting edge. An arcuate small protrusion is formed on the bisector of each nose portion. A narrow groove is formed in the small protrusion. Thin chips, which are produced while the feed rate is low, are curled and broken by the groove formed in the protrusion. Thick chips, which are produced while the feed rate is high, are guided along the grooves and collide with an edge of a side wall of the center land. Thus, thick chips are also smoothly curled and broken by the edge.