Patents by Inventor Shinya FUKAYAMA

Shinya FUKAYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607964
    Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 31, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Yukifumi Oyama, Keisuke Taniguchi
  • Patent number: 10217676
    Abstract: A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: February 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Naoyuki Komuta, Hiroshi Watabe
  • Publication number: 20170069551
    Abstract: A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.
    Type: Application
    Filed: August 10, 2016
    Publication date: March 9, 2017
    Inventors: Shinya FUKAYAMA, Naoyuki KOMUTA, Hiroshi WATABE
  • Patent number: 9570414
    Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Tsukiyama, Masatoshi Fukuda, Yukifumi Oyama, Shinya Fukayama
  • Publication number: 20160351541
    Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.
    Type: Application
    Filed: March 4, 2016
    Publication date: December 1, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Keisuke TANIGUCHI
  • Patent number: 9448065
    Abstract: A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: September 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Fukayama, Yukifumi Oyama, Kazuhiro Murakami
  • Publication number: 20160111317
    Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Satoshi TSUKIYAMA, Masatoshi FUKUDA
  • Publication number: 20160079102
    Abstract: A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.
    Type: Application
    Filed: March 2, 2015
    Publication date: March 17, 2016
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Kazuhiro MURAKAMI
  • Publication number: 20150123270
    Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.
    Type: Application
    Filed: September 2, 2014
    Publication date: May 7, 2015
    Inventors: Satoshi TSUKIYAMA, Masatoshi FUKUDA, Yukifumi OYAMA, Shinya FUKAYAMA
  • Publication number: 20150069110
    Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.
    Type: Application
    Filed: February 24, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya FUKAYAMA, Yukifumi OYAMA, Satoshi TSUKIYAMA, Masatoshi FUKUDA
  • Publication number: 20150069634
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: March 2, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukifumi OYAMA, Hideko MUKAIDA, Masatoshi FUKUDA, Satoshi TSUKIYAMA, Shinya FUKAYAMA