Abstract: In a control circuit that controls an interleaved power supply, a clock generator generates a clock pulse having a predetermined frequency. A signal doubler generates a master switch on-interval pulse signal indicating information concerning an on-interval of the master switch based on the clock pulse and a master drive pulse signal that drives the master switch, and generates a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal. An edge pulse generator generates a first edge pulse signal based on the master drive pulse signal, and generates a second edge pulse signal based on the doubled duty pulse signal. A slave drive pulse signal generator generates, based on the first and second edge pulse signals, a slave drive pulse signal that drives the slave switch so that an on-interval of the slave switch is identical to that of the master switch.

Abstract: A control circuit that controls an interleaved power supply, and an interleaved power supply including that control circuit, which are unlikely to be affected by a variation among components and are suitable for mass production, are provided. The clock generator generates a clock pulse having a predetermined frequency. The signal doubler generates a master switch on-interval pulse signal indicating information concerning an on-interval of the master switch based on the clock pulse and a master drive pulse signal that switch-drives the master switch of the master converter, and generates a doubled duty pulse signal having a duty that is double that of the master switch on-interval pulse signal. The edge pulse generator generates a first edge pulse signal based on the master drive pulse signal, and generates a second edge pulse signal based on the doubled duty pulse signal.