Patents by Inventor Shinya Iwasa
Shinya Iwasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9437265Abstract: Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode.Type: GrantFiled: August 18, 2014Date of Patent: September 6, 2016Assignee: Micron Technology, Inc.Inventors: Shinya Iwasa, Migaku Kobayashi
-
Patent number: 9236388Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.Type: GrantFiled: May 8, 2014Date of Patent: January 12, 2016Assignee: PS4 Luxco S.a.r.l.Inventor: Shinya Iwasa
-
Publication number: 20150055394Abstract: A semiconductor device comprises a semiconductor substrate including first and second regions that have different conductivity types from each other; an isolation region extending continuously over the first and second regions and having a shallow trench covered by a field insulator; first and second active regions placed in respective first and second regions and being each surrounded by the isolation region; a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region via the isolation region, the gate groove being shallower than the shallow trench; a cap insulating film disposed in an upper portion of the gate groove so as to cover an upper surface of the gate electrode; first and second transistors placed in respective first and second active regions and sharing the gate electrode; and a logic circuit including the first and second transistors connected in series.Type: ApplicationFiled: August 18, 2014Publication date: February 26, 2015Inventors: Shinya IWASA, Migaku KOBAYASHI
-
Publication number: 20140239389Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.Type: ApplicationFiled: May 8, 2014Publication date: August 28, 2014Applicant: PS4 Luxco S.a.r.l.Inventor: Shinya IWASA
-
Patent number: 8759844Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.Type: GrantFiled: May 27, 2011Date of Patent: June 24, 2014Inventor: Shinya Iwasa
-
Publication number: 20110291168Abstract: Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer (10) in region B is also grown from the surface of a substrate which is exposed when only the surface of STI (2) in region B is drawn back, so that a facet (F) of the semiconductor layer 10 is formed outside the active area, followed by ion-implantation to form a high density diffusion layer (11) in region B. Accordingly, short circuit between semiconductor layers on source/drain electrodes of transistors in region A is prevented, and uniformity of the junction depth of the layer (11) of the source/drain electrodes including an ESD region in a transistor of region B is obtained, thereby restricting the short channel effect.Type: ApplicationFiled: May 27, 2011Publication date: December 1, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Shinya IWASA
-
Patent number: 8003472Abstract: When transistors having different gate lengths are formed on one substrate and an ESD structure is applied to at least a transistor having longer gate length, a method including: depositing a gate insulating film and a gate electrode material layer on the substrate; forming a first gate electrode having a longer gate length in a first region; forming a first insulating film on a whole surface; forming a second gate electrode including the first insulating film and having a shorter gate length in a second region; forming a second insulating film on a whole surface; forming second sidewalls made of the second insulating film on sidewalls of the second gate electrode; forming first sidewalls made of the first and second insulating films on sidewalls of the first gate electrode; forming a selectively epitaxially grown layer on at least exposed substrate of the first region and implanting ions into the substrate via the selectively epitaxially grown layer, thereby forming an ESD structure.Type: GrantFiled: August 13, 2010Date of Patent: August 23, 2011Assignee: Elpida Memory, Inc.Inventor: Shinya Iwasa
-
Publication number: 20110053330Abstract: When transistors having different gate lengths are formed on one substrate and an ESD structure is applied to at least a transistor having longer gate length, a method including: depositing a gate insulating film and a gate electrode material layer on the substrate; forming a first gate electrode having a longer gate length in a first region; forming a first insulating film on a whole surface; forming a second gate electrode including the first insulating film and having a shorter gate length in a second region; forming a second insulating film on a whole surface; forming second sidewalls made of the second insulating film on sidewalls of the second gate electrode; forming first sidewalls made of the first and second insulating films on sidewalls of the first gate electrode; forming a selectively epitaxially grown layer on at least exposed substrate of the first region and implanting ions into the substrate via the selectively epitaxially grown layer, thereby forming an ESD structure.Type: ApplicationFiled: August 13, 2010Publication date: March 3, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Shinya IWASA
-
Patent number: 6541335Abstract: A semiconductor device has such a configuration that a contact hole is formed in a fourth inter-layer insulator film which covers an upper electrode of a capacitor, to expose part of the upper electrode; and below the contact hole, a trench covered by a capacitive insulator film formed in a trench is formed larger than the contact hole in width, to have therein a polycrystalline silicon film which constitutes the upper electrode.Type: GrantFiled: September 20, 2001Date of Patent: April 1, 2003Assignees: NEC Corporation, NEC Electronics CorporationInventor: Shinya Iwasa
-
Patent number: 6362024Abstract: In a method of manufacturing a semiconductor memory device, a first interlayer insulating film is formed to have at least one fuse therein. An etching stopper film is formed on the first interlayer insulating film. A first layer is formed on the etching stopper film. The first layer is etched to the etching stopper film using a first mask. Then, the etching stopper film is etched to produce a fuse cutting window.Type: GrantFiled: November 15, 1999Date of Patent: March 26, 2002Assignee: NEC CorporationInventors: Makoto Kotou, Shinya Iwasa
-
Publication number: 20020013026Abstract: A semiconductor device has such a configuration that a contact hole is formed in a fourth inter-layer insulator film which covers an upper electrode of a capacitor, to expose part of the upper electrode; and below the contact hole, a trench covered by a capacitive insulator film formed in a trench is formed larger than the contact hole in width, to have therein a polycrystalline silicon film which constitutes the upper electrode.Type: ApplicationFiled: September 20, 2001Publication date: January 31, 2002Applicant: NEC CorporationInventor: Shinya Iwasa
-
Patent number: 6313497Abstract: A semiconductor device has such a configuration that a contact hole is formed in a fourth inter-layer insulator film which covers an upper electrode of a capacitor, to expose part of the upper electrode; and below the contact hole, a trench covered by a capacitive insulator film formed in a trench is formed larger than the contact hole in width, to have therein a polycrystalline silicon film which constitutes the upper electrode.Type: GrantFiled: February 15, 2000Date of Patent: November 6, 2001Assignee: NEC CorporationInventor: Shinya Iwasa
-
Patent number: 5955788Abstract: A semiconductor device having metal wirings in two or more layers has a slit formed in the metal wiring which is a lower layer, and a SOG film flows into the slit while forming the SOG film. The film thickness of the SOG film formed on the metal wiring of a large area differs little from that of the SOG film formed on the metal wiring of a small area. Therefore, a grade of flatness of an interlayer insulating film disposed between the metal wirings is not deteriorated. A humidity resistant property and an electromigration resistant property are not degraded.Type: GrantFiled: January 13, 1997Date of Patent: September 21, 1999Assignee: NEC CorporationInventor: Shinya Iwasa
-
Patent number: 5478768Abstract: In a semiconductor memory device comprising a plurality of memory cells each including a switching transistor having a gate electrode and source/drain regions, one or more interlayer insulating layers are deposited on the surface of the substrate. A first conductive layer is deposited on the entire surface of the interlayer insulating layers. The first conductive layer has an etching rate slower than that of the interlayer insulating layers. A first coating film is formed on the entire surface of the first conductive layers. The first coating film and the first conductive layer on the source region are selectively removed by photolithography process to form an opening. A second coating film is formed in the opening to form a spacer on the inner side wall of the opening. The second coating film has an etching rate slower than that of the interlayer insulating layer. A contact hole is made on the source region using the first conductive layer and the spacer as a mask.Type: GrantFiled: September 30, 1994Date of Patent: December 26, 1995Assignee: NEC CorporationInventor: Shinya Iwasa
-
Patent number: 5361234Abstract: A semiconductor memory device comprises a plurality of word lines, a plurality of digit lines, a peripheral circuit area and a memory cell array area. The memory cell array area comprises a semiconductor substrate having a surface in which field oxide films are selectively formed, a plurality of operational memory cells arrayed on active regions within the memory cell array area, each of which includes a stacked capacitor and a switching transistor, and a plurality of dummy capacitors arranged within the memory cell array area at an adjacent portion to a boundary area between the memory cell array area and the peripheral circuit area. The dummy capacitor is to receive affections caused by an inferiority of the accuracy of patterning by a photolithography in replacement of the operational memory cells. The dummy capacitor is so formed over the field oxide film as to prevent said digit line at said boundary area to have a rapid slope or a large difference in level.Type: GrantFiled: March 26, 1993Date of Patent: November 1, 1994Assignee: NEC CorporationInventor: Shinya Iwasa