Patents by Inventor Shinya Kashima

Shinya Kashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116278
    Abstract: This layered film includes a base layer and a sealant layer that becomes one outermost surface of the layered film. The base layer contains 77 to 99 parts by mass of a high-density polyethylene having a density of 0.942 to 0.970 g/cm3 and a melt mass-flow rate of 0.1 to 3.0 g/10 min under conditions of a temperature of 190° C. and a load of 2.16 kg and 1 to 23 parts by mass of an ultra-high-molecular-weight polyethylene having a density of 0.930 to 0.960 g/cm3 in a total of 100 parts by mass.
    Type: Application
    Filed: January 19, 2022
    Publication date: April 11, 2024
    Inventors: Kousuke Kashima, Toshihiko Mori, Shinya Ozaki
  • Patent number: 11864316
    Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 2, 2024
    Assignee: FUJIKURA LTD.
    Inventors: Naoki Oyaizu, Yusuke Fujita, Toshiaki Inoue, Shinya Kashima
  • Publication number: 20220361330
    Abstract: A wiring substrate includes a first insulating layer, a first conductor layer, and a plurality of filled vias. The first insulating layer has a first surface and a second surface positioned on a side opposite to the first surface. The first conductor layer is formed on the first surface of the first insulating layer. The plurality of filled vias are formed inside the first insulating layer. The plurality of filled vias each have a structure in which a via hole penetrating the first insulating layer is filled with a metal. The first conductor layer includes a pad. The pad overlaps the plurality of filled vias in a plan view from a thickness direction of the first insulating layer and is connected to the plurality of filled vias.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 10, 2022
    Applicant: Fujikura Ltd.
    Inventors: Naoki Oyaizu, Yusuke Fujita, Toshiaki Inoue, Shinya Kashima