Patents by Inventor Shinya Kishida

Shinya Kishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Network security device, network management method, and non-transitory computer-readable medium
    Patent number: 10270653
    Abstract: There is provided a network security device comprising: a processor programmed to: identify a terminal for which communication is to be blocked; detect Dynamic Host Configuration Protocol (DHCP) request information which is requesting a DHCP server to allocate an IP address; send out a message meaning that the IP address requested by the DHCP request information is unusable; and transmit, if the detected DHCP request information is sent by the identified terminal, DHCP release information for releasing the IP address requested by this DHCP request information to the DHCP server.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 23, 2019
    Assignee: PFU LIMITED
    Inventors: Shinya Kishida, Natsuki Kadoya, Toru Nakazono
  • NETWORK SECURITY DEVICE, NETWORK MANAGEMENT METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM
    Publication number: 20170207965
    Abstract: There is provided a network security device comprising: a processor programmed to: identify a terminal for which communication is to be blocked; detect Dynamic Host Configuration Protocol (DHCP) request information which is requesting a DHCP server to allocate an IP address; send out a message meaning that the IP address requested by the DHCP request information is unusable; and transmit, if the detected DHCP request information is sent by the identified terminal, DHCP release information for releasing the IP address requested by this DHCP request information to the DHCP server.
    Type: Application
    Filed: April 27, 2016
    Publication date: July 20, 2017
    Inventors: Shinya KISHIDA, Natsuki KADOYA, Toru NAKAZONO
  • Single instruction decode circuit for decoding instruction from memory and instructions from an instruction generation circuit
    Patent number: 8255672
    Abstract: A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 28, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Iwao Honda, Shinya Kishida
  • Processor
    Publication number: 20080301401
    Abstract: A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 4, 2008
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Iwao Honda, Shinya Kishida