Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: A memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller is configured to: after transmitting a write command and an address to the nonvolatile memory via a first signal line, transmit dummy data to the nonvolatile memory via the first signal line during at least a portion of a period that is between when the address is transmitted via the first signal line and when write data of the write command is transmitted via the first signal line, and after transmitting the dummy data via the first signal line, transmit a data strobe signal to the nonvolatile memory via a second signal line and transmit the write data of the write command to the nonvolatile memory via the first signal line in synchronization with the data strobe signal.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: Provided is an audio signal processing apparatus including: a first buffer configured to temporarily store an audio signal; a feedback path whose start point and end point are located close to an output side of the first buffer; and a second buffer connected in the feedback path and configured to temporarily store the audio signal.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.

Abstract: A memory system includes a first memory chip, and a controller that includes a first circuit, a second circuit, and a third circuit. The third circuit is configured to manage a first differential power consumption value that is a difference between first and second power consumption values. The first power consumption value is on first power that the first memory chip consumes while executing a first operation. The second power consumption value is on second power that the first memory chip consumes when suspending the first operation. The third circuit is configured to determine whether causing the first memory chip to suspend the first operation to execute a second operation is possible based on the first differential power consumption value.

Abstract: A memory system includes: a plurality of nonvolatile memories; a controller connected to the plurality of nonvolatile memories via a plurality of channels that includes a plurality of memory physical layer circuits arranged corresponding to the plurality of channels, respectively, one or more pads for calibration corresponding to the plurality of memory physical layer circuits, and a processor that controls the plurality of memory physical layer circuits. A single reference resistor is connected to the plurality of memory physical layer circuits via the pad. An output based on a ZQ calibration of the plurality of memory physical layer circuits is wired-OR connected to the single reference resistor via the one or more pads. The processor performs a calibration for each of the plurality of memory physical layer circuits in a time division manner using the single reference resistor.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: A memory system includes a first memory chip, and a controller that includes a first circuit, a second circuit, and a third circuit. The third circuit is configured to manage a first differential power consumption value that is a difference between first and second power consumption values. The first power consumption value is on first power that the first memory chip consumes while executing a first operation. The second power consumption value is on second power that the first memory chip consumes when suspending the first operation. The third circuit is configured to determine whether causing the first memory chip to suspend the first operation to execute a second operation is possible based on the first differential power consumption value.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: In a probe apparatus for performing an electrical measurement by bringing a probe into contact with an inspection target substrate, a transfer table is provided with a needle mark transfer member to which a needle mark of the probe is transferred by a contact with the probe. The needle mark transfer member includes a polyimide resin. A movement mechanism is able to move the needle mark transfer member provided on the transfer table to a contact position where the needle mark transfer member is brought into contact with the probe.

Abstract: According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.

Abstract: In a method for thermal stabilization of a probe card, a probe card is adjusted to a prescribed temperature in a short time by making a heat source directly contact the probe card and is accurately determined whether the probe card is thermally stable. A heat transfer substrate is mounted on a mounting table. The temperature of the heat transfer substrate is adjusted through the mounting table. The mounting table is raised, and a plurality of probes is brought into contact with the heat transfer substrate at a prescribed target load. The contact load between the heat transfer substrate and the probes, which changes according to the thermal changes in the probe card, is detected. The mounting table is controlled vertically through a vertical drive mechanism such that the contact load becomes the target load until the probe card is thermally stable.

Abstract: In a method for thermal stabilization of a probe card, a probe card is adjusted to a prescribed temperature in a short time by making a heat source directly contact the probe card and is accurately determined whether the probe card is thermally stable. A heat transfer substrate is mounted on a mounting table. The temperature of the heat transfer substrate is adjusted through the mounting table. The mounting table is raised, and a plurality of probes is brought into contact with the heat transfer substrate at a prescribed target load. The contact load between the heat transfer substrate and the probes, which changes according to the thermal changes in the probe card, is detected. The mounting table is controlled vertically through a vertical drive mechanism such that the contact load becomes the target load until the probe card is thermally stable.

Abstract: A probe apparatus includes a movable mounting table for supporting an object to be tested; a probe card disposed above the mounting table and having a plurality of probes to come into contact with electrodes of the object; a support body for supporting the probe card; and a control unit for controlling the mounting table. Electrical characteristics of the object are tested based on a signal from a tester by bringing the object and the probes into electrical contact with each other by overdriving the mounting table in a state where a test head is electrically connected with the probe card by a predetermined load. Further, one or more distance measuring devices for measuring a current overdriving amount of the mounting table are provided at one or more locations of the test head or the probe card.

Abstract: A probe apparatus includes a movable mounting table for supporting an object to be tested; a probe card disposed above the mounting table and having a plurality of probes to come into contact with electrodes of the object; a support body for supporting the probe card; and a control unit for controlling the mounting table. Electrical characteristics of the object are tested based on a signal from a tester by bringing the object and the probes into electrical contact with each other by overdriving the mounting table in a state where a test head is electrically connected with the probe card by a predetermined load. Further, one or more distance measuring devices for measuring a current overdriving amount of the mounting table are provided at one or more locations of the test head or the probe card.

Abstract: A cross fader unit, a mixer and a program which can achieve various music expressions with a simple manipulation are provided. A cross fader unit CF has an adjustment device by band 50 that adjusts a mixing rate of the audio signal in each frequency band by moving a plurality of the manipulation members each of which is a manipulation member by frequency band divided into a plurality of bands of the audio signal on a corresponding line 52.