Patents by Inventor Shinya Kuribayashi

Shinya Kuribayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-processor system and message transferring method in the same
    Patent number: 7613197
    Abstract: A multi-processor system includes a plurality of processors; and a memory section connected with the plurality of processors and configured to store a message transmitted from each of the plurality of processor to another. The memory section has a plurality of priority buffer regions corresponding to a plurality of priority levels, and the message is classified based on a priority level allocated to the message. Each of the plurality of priority buffer regions stores the message having the priority level corresponding to the buffer region.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: November 3, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Shinya Kuribayashi
  • Multi-processor system and message transferring method in the same
    Publication number: 20060248218
    Abstract: A multi-processor system includes a plurality of processors and a memory section. The memory section is configured to be provided to store a message sent from one of the plurality of processors to another of the plurality of processors. The memory section includes a plurality of first buffer regions. Each of the plurality of first buffer regions corresponds to one of the plurality of processors on a message reception side.
    Type: Application
    Filed: April 25, 2006
    Publication date: November 2, 2006
    Inventor: Shinya Kuribayashi
  • Multi-processor system and message transferring method in the same
    Publication number: 20060242257
    Abstract: A multi-processor system includes a plurality of processors; and a memory section connected with the plurality of processors and configured to store a message transmitted from each of the plurality of processor to another. The memory section has a plurality of priority buffer regions corresponding to a plurality of priority levels, and the message is classified based on a priority level allocated to the message. Each of the plurality of priority buffer regions stores the message having the priority level corresponding to the buffer region.
    Type: Application
    Filed: April 19, 2006
    Publication date: October 26, 2006
    Inventor: Shinya Kuribayashi