Abstract: Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an n+ drain layer; a parallel pn layer including n? drift and p pillar layers joined alternately; a composite layer including a p base layer and an n+ source layer, the n+ drain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n+ source layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the n? drift layer.

Abstract: Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an n+ drain layer; a parallel pn layer including n? drift and p pillar layers joined alternately; a composite layer including a p base layer and an n+ source layer, the n+ drain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n+ source layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the n? drift layer.

Abstract: An n-channel BiMOS semiconductor device having a trench gate structure includes an n+ drain layer; a parallel pn layer including n? drift and p pillar layers joined alternately; and a composite layer including a p base layer and an n+ source layer, in which the n+ drain layer, the parallel pn layer, and the composite layer are provided in order.

Abstract: Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application device 1 is configured to have a contacting section having a plurality of projections 21 for contacting a contact region 24 inside an active region 23 of a semiconductor element 22 and applying the test current thereto, and a pressing section 3 which presses the contacting section 2 against the semiconductor element 22 such that each projection 21 contacts the contact region 24. A plurality of the projections 21 are arranged such that an arrangement density of outside projections 21 is larger than the arrangement density of inside projections 21.

Abstract: Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application device 1 is configured to have a contacting section having a plurality of projections 21 for contacting a contact region 24 inside an active region 23 of a semiconductor element 22 and applying the test current thereto, and a pressing section 3 which presses the contacting section 2 against the semiconductor element 22 such that each projection 21 contacts the contact region 24. A plurality of the projections 21 are arranged such that an arrangement density of outside projections 21 is larger than the arrangement density of inside projections 21.