Patents by Inventor Shinya Maruoka

Shinya Maruoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7812893
    Abstract: An active matrix substrate suppresses reduction in production yield and increase in production steps and simultaneously permits both sufficient securing of a storage capacity and improvement of an aperture ratio of a pixel. The active matrix substrate is an active matrix substrate and includes a thin film transistor disposed at an intersection of a scanning signal line with a data signal line on a substrate, the thin film transistor including a gate electrode connected to the scanning signal line, a source electrode connected to the data signal line, and a drain electrode connected to a drain lead-out wiring; a storage capacitor upper electrode connected to the drain lead-out wiring and a pixel electrode; and a storage capacitor wiring overlapping with the storage capacitor upper electrode through an insulating film, wherein the storage capacitor wiring has an extending portion overlapping with the drain lead-out wiring through the insulating film.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: October 12, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Toshihide Tsubata, Tsuyoshi Tokuda, Kenji Enda, Yoshinori Shimada, Shinya Maruoka
  • Publication number: 20090073335
    Abstract: An active matrix substrate suppresses reduction in production yield and increase in production steps and simultaneously permits both sufficient securing of a storage capacity and improvement of an aperture ratio of a pixel. The active matrix substrate is an active matrix substrate and includes a thin film transistor disposed at an intersection of a scanning signal line with a data signal line on a substrate, the thin film transistor including a gate electrode connected to the scanning signal line, a source electrode connected to the data signal line, and a drain electrode connected to a drain lead-out wiring; a storage capacitor upper electrode connected to the drain lead-out wiring and a pixel electrode; and a storage capacitor wiring overlapping with the storage capacitor upper electrode through an insulating film, wherein the storage capacitor wiring has an extending portion overlapping with the drain lead-out wiring through the insulating film.
    Type: Application
    Filed: September 20, 2005
    Publication date: March 19, 2009
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Toshifumi Yagi, Toshihide Tsubata, Tsuyoshi Tokuda, Kenji Enda, Yoshinori Shimada, Shinya Maruoka