Abstract: A device layer contains a semiconductor element in part of a region thereof. An insulating layer is on one surface of the device layer. A support substrate including a semiconductor is on a surface of the insulating layer on an opposite side from a side where the device layer is disposed. The support substrate has an opening overlapping a semiconductor element region in which the semiconductor element is formed in plan view and extending from a bottom surface of the support substrate to the insulating layer, the bottom surface being on an opposite side from a side where the insulating layer is disposed. An insulating heat dissipation layer contacts the insulating layer in a region encompassed by the opening in plan view and has a thermal conductivity higher than that of the insulating layer.

Abstract: There is provided a capacitor including a dielectric layer having a first plane, a second plane opposite to the first plane, and a plurality of through-holes communicated with the first plane and the second plane; a first external conductor layer disposed on a part of the first plane; a second external conductor layer disposed on the second plane; a third external conductor layer disposed on another part of the first plane; a first internal conductor housed in a part of a plurality of the through-holes and connected to the first external conductor layer; a second internal conductor housed in another part of a plurality of the through-holes and connected to the second external conductor layer; and a third internal conductor housed in the other part of a plurality of the through-holes and connected to the second external conductor layer and the third external conductor layer.