Patents by Inventor SHINYA NAMIOKA

SHINYA NAMIOKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a high-speed receiver being capable of adjusting timing skew for multi-level signal and testing equipment including the receiver
    Patent number: 10855497
    Abstract: A semiconductor device including a signal generator and decoding and timing skew adjusting circuit is provided. The signal generator is configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m?1) single level signals having two signal levels. The decoding and timing skew adjusting circuit is configured to receive the single level signals, perform a predefined operation on the single level signals to generate an output signal, and compensate for timing skew between the n multi-level signals, using the single level signals. The n and m are natural numbers, where n>=2 and m>=3.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoshihiko Hayashi, Shinya Namioka, Chang Eun Lee, Sung-Yeol Kim, Si Young Koh, Hyung-Sun Ryu, Jang Yeob Lee, Shin Ki Jeong
  • SEMICONDUCTOR DEVICE INCLUDING A HIGH-SPEED RECEIVER BEING CAPABLE OF ADJUSTING TIMING SKEW FOR MULTI-LEVEL SIGNAL AND TESTING EQUIPMENT INCLUDING THE RECEIVER
    Publication number: 20190363914
    Abstract: A semiconductor device including a signal generator and decoding and timing skew adjusting circuit is provided. The signal generator is configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m?1) single level signals having two signal levels. The decoding and timing skew adjusting circuit is configured to receive the single level signals, perform a predefined operation on the single level signals to generate an output signal, and compensate for timing skew between the n multi-level signals, using the single level signals. The n and m are natural numbers, where n>=2 and m>=3.
    Type: Application
    Filed: February 28, 2019
    Publication date: November 28, 2019
    Inventors: YOSHIHIKO HAYASHI, SHINYA NAMIOKA, CHANG EUN LEE, SUNG-YEOL KIM, SI YOUNG KOH, HYUNG-SUN RYU, JANG YEOB LEE, SHIN Kl JEONG