Abstract: Disclosed is a solid-state imaging device wherein optical information of a number of photo-electric conversion elements arranged in a matrix is read into vertical signal lines by a vertical shift register and then the optical information on the vertical signal lines is horizontally scanned by a horizontal register of a charge transfer device. Bias charge storage means and quasi-signal sweep-out drains are disposed between the horizontal register and the vertical signal lines, and a bias charge input means is arranged in the horizontal register. In order to ensure high efficiency in transferring signals between the vertical lines to the storage means, the sweep-out drains and the charge transfer device, it is arranged for bias charges to be provided at each stage of transfer. Thus, bias charges supplied from the storage means are used to transfer charges from the vertical lines to the storage means.

Abstract: A solid-state imaging device is provided which employs CCDs as vertical shift registers and a horizontal shift register for vertically and horizontally scanning and reading out a large number of photoelectric elements arrayed in a two-dimensional plane. The imaging device is characterized in that the photoelectric elements of each column arranged between the vertical shift registers are alternately connected to the right and left vertical shift registers. This results in the resolution of the device being enhanced sharply.

Abstract: In a solid state image pick-up device of the type comprising a first semiconductor layer including a photoelectric conversion element array, and vertical and horizontal switching elements adapted to select the photoelectric conversion elements, a second semiconductor layer including a horizontal shift register for selecting the horizontal switching elements, a third semiconductor layer including a vertical shift register for selecting the vertical switching elements, the first, second and third semiconductor layers are insulated from each other, and gate voltage V.sub.SMOS.L impressed upon a gate electrode of a not selected horizontal switching element is made to satisfy a relation V.sub.SMOS.L .gtoreq.V.sub.WPD +F.sub.FB where V.sub.WPD represents a potential of the first semiconductor layer, and V.sub.FB a flat band voltage beneath gate electrodes of the horizontal switching elements.

Abstract: A solid-state imaging device comprises an array of picture elements and a horizontal CTD shift register. In a horizontal blanking period, two or more sets of signals from vertical signal output lines coupled to the picture element array are stored in the horizontal CTD shift register. In a horizontal scanning period, the horizontal CTD shift register operates in a 3-phase (or 4-phase) driving fashion to deliver picture image information signal to its output part.

Abstract: A solid-state imaging device comprises a plurality of photodiodes arranged in a matrix form in the same semiconductor substrate, horizontal and vertical switching elements for selecting the photodiodes, horizontal and vertical shift registers for supplying scan pulses to the horizontal and vertical switching elements, and an interlace circuit for simultaneously selecting two vertical gate lines to simultaneously read two picture element rows. A buffer circuit is inserted between the interlace circuit and the vertical gate lines for changing a potential level of one of the two selected vertical gate lines from a high level to a low level prior to changing the potential level of the other vertical gate line.

Abstract: A solid state image pickup device having a plurality of solid state elements in a two-dimensional array so as to form picture cells. Each solid state element includes a photoelectric converting element and a switching field effect transistor to permit scanning of the elements by scanners. To counteract noise and blooming, a second field effect transistor acting as an amplifier is connected between the photoelectric converting element and the switching field effect transistor. A third field effect transistor is coupled to the photoelectric converting element for resetting the same.

Abstract: In a solid-state imaging device having a plurality of photodiodes which are arrayed in two dimensions on an identical semiconductor body, a group of horizontal switching elements and a group of vertical switching elements which pick up the photodiodes, and a horizontal scanning circuit and a vertical scanning circuit which impress scanning pulses on the horizontal and vertical switching elements respectively, and having an interlaced scanning mechanism which picks up a plurality of vertical scanning lines by means of interlace switching elements so as to permit horizontal scanning of scanning lines of a plurality of rows; a solid-state imaging device characterized in that said interlaced scanning mechanism includes insulated-gate field effect transistors for recovering voltage levels of the scanning pulses having undergone voltage drops due to the interlace switching elements.

Abstract: A signal processing circuit for use in a solid-state camera comprising a sensor for deriving an electrical signal from the camera, a preamplifier for amplifying the output of the sensor and an integrator for integrating the output of the preamplifier. A specific circuit arrangement is provided for the preamplifier to narrow the bandwidth of the preamplifier, so that an abnormal increase of noise in the electrical signal is effectively suppressed.

Abstract: A solid-state imaging device wherein a MOS sensor is employed for a photosensor part, a CTD shift register is employed for a read-out circuit, first and second transfer gates are connected between vertical signal output lines and the CTD, and a reset gate is connected between a juncture of the first and second transfer gates and a reset voltage line. A method is adopted in which signal outputs of a plurality of rows are transferred to the CTD in a horizontal blanking period, and signals of a plurality of rows are simultaneously read out in a horizontal scanning period. At the signal transfer, bias charges are dumped into the vertical signal output lines from the CTD, and mixed charges consisting of the bias charges and signal charges are transferred to the CTD. Thereafter, the signals are read out.

Abstract: This invention provides a signal processing circuit of a solid-state imaging device utilizing discontinuous scanning pulses having fixed interval times, and with a fixed pattern noise-eliminating circuit of high performance. In the signal processing circuit of this invention, switching elements are disposed in a feedback circuit of a signal amplifier (for example, pre-amplifier) and at an output of the signal amplifier, whereby the fixed pattern noise is suppressed so as to attain a high signal-to-noise ratio.

Abstract: In a solid-state imaging device comprising photodiodes arranged in a two-dimensional array, vertical and horizontal switching MOS transistors for selecting the photodiodes, vertical and horizontal scanning circuits for supplying scanning pulses to the gate electrodes of the vertical and horizontal switching MOS transistors respectively, a signal switching gate MOS transistor is connected between a signal output terminal and a horizontal signal output line connecting in common the horizontal switching MOS transistors.

Abstract: A circuit for generating scanning pulses comprising a plurality of stages of basic circuits connected in series, said each basic circuit comprising first, second and third insulated gate field-effect transistors (MISTs) each of which has first and second terminals each being either of source and drain terminals and a gate terminal, said first terminal of said first MIST being used as a clock pulse-applying terminal, said gate terminal of said first MIST being used as an input terminal, said second terminal of said first MIST and said first terminal and said gate terminal of said second MIST being connected and used as a scanning pulse output terminal, said second terminal of said second MIST and said first terminal of said third MIST being connected and used as an output terminal, said second terminal of said third MIST being used as a ground terminal, said gate terminal of said third MIST being used as a feedback input terminal.

Abstract: A solid-state imaging device which is horizontally scanned by a discontinuous scanning pulse train, wherein an output signal of the device is integrated by a signal processing circuit which comprises an emitter follower (source follower) circuit and a capacitor disposed in parallel with the emitter follower (source follower) circuit, whereby noise components are canceled so as to derive only a video signal. With this solid-state imaging device, fixed pattern noise can be eliminated, and a good picture quality can be achieved.

Abstract: In a solid-state imaging device having on an identical semiconductor substrate a plurality of photodiodes which are arrayed in two dimensions, vertical and horizontal switching MOSFETs which select the positions of the photodiodes, and vertical and horizontal scanning circuits which provide scanning pulses for controlling the operations of the vertical and horizontal switching MOSFETs; the improvement therein comprising a clamping circuit which is made up of a diode, a MOSFET or the like and which is disposed between the photodiode and a vertical scanning line of the succeeding stage, so that excess charges overflowing the photodiode are drawn out from the vertical scanning line through the clamping circuit, whereby the blooming can be prevented.

Abstract: In a solid-state imaging device having, in one major surface region of a semiconductor substrate, photoelectric conversion elements which are disposed in a two-dimensional array, vertical switching metal-insulator-semiconductor field effect transistors and horizontal switching metal-insulator-semiconductor field effect transistors which select the photoelectric conversion elements, and vertical and horizontal scanning circuits which turn the switching transistors "on" and "off," a solid-state imaging device characterized in that the vertical switching metal-insulator-semiconductor field effect transistors which are not selected are placed into a deeper cutoff state, i.e., the major surface regions of the semiconductor substrate corresponding to gate electrodes of these vertical switching metal-insulator-semiconductor field effect transistors are placed at an accumulation level.

Abstract: In a solid-state imaging device wherein a plurality of photoelectric conversion elements, horizontal and vertical scanning circuits for addressing the photoelectric conversion elements, and horizontal and vertical switching transistors are comprised in a major surface region of an N (or P)-type semiconductor body, a solid-state imaging device characterized in that a plurality of P (or N)-type impurity layers isolated from one another are disposed in the major surface region of the semiconductor body, that the switching transistors and the photoelectric conversion elements are integrated in one of the impurity layers, the horizontal scanning circuit being integrated in another impurity layer, the vertical scanning circuit being integrated in still another impurity layer, and that predetermined voltages are applied to electrodes disposed on the respective impurity layers.

Abstract: In a semiconductor photoelectric device comprising a plurality of photodiodes, MOS transistor switches and signal output means which are provided on a semiconductor substrate, a solid-state imaging device characterized in that said each photodiode is constructed of a PN-junction diode and an MIS or MOS diode. Means are provided for permitting incident light to fall on only the PN-junction diode.

Abstract: A charge transfer device is provided with a clock pulse generator circuit driving simultaneously at least two charge transfer arrays, which is divided into at least two blocks arranged so as to confine the at least two lines of charge transfer arrays therebetween.

Abstract: In a charge transfer semiconductor device majority carriers are transferred within a semiconductor body on a substrate from means for introducing majority carriers to means for detecting transferred majority carriers by applying pulsed voltages to a series of electrodes disposed on an insulating layer which is disposed on one surface of the semiconductor body between the introducing means and the detecting means. Depletion regions are formed within the semiconductor body, so that one end of a depletion region below one electrode reaches the substrate and another end of a depletion region below an electrode next to the one electrode does not reach the substrate, whereby majority carriers below the one electrode are pushed out below the next electrode.