Patents by Inventor Shinya OHIRA

Shinya OHIRA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Active-matrix substrate and display device
    Patent number: 10957268
    Abstract: An active-matrix substrate according to an embodiment of the present invention includes a plurality of first TFTs that are arranged within a display area, an inorganic insulating layer that covers the plurality of first TFTs, an organic insulating layer that is provided on the inorganic insulating layer, a plurality of second TFTs that are arranged within a non-display area, and a source and gate metal connection portion that is positioned within the non-display area, a first conductive layer that is formed from an identical conductive film with a gate wiring line and a second conductive layer that is formed from an identical conductive film with a source wiring line being connected to each other at the source and gate metal connection portion. Each of the plurality of first TFTs is an oxide semiconductor TFT. At least one second TFT among the plurality of second TFTs is covered with the organic insulating layer. The source and gate metal connection portion is not covered with the organic insulating layer.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 23, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Kikuchi, Hajime Imai, Takashi Terauchi, Shinya Ohira, Isao Ogasawara, Satoshi Horiuchi
  • ACTIVE-MATRIX SUBSTRATE AND DISPLAY DEVICE
    Publication number: 20190333461
    Abstract: An active-matrix substrate according to an embodiment of the present invention includes a plurality of first TFTs that are arranged within a display area, an inorganic insulating layer that covers the plurality of first TFTs, an organic insulating layer that is provided on the inorganic insulating layer, a plurality of second TFTs that are arranged within a non-display area, and a source and gate metal connection portion that is positioned within the non-display area, a first conductive layer that is formed from an identical conductive film with a gate wiring line and a second conductive layer that is formed from an identical conductive film with a source wiring line being connected to each other at the source and gate metal connection portion. Each of the plurality of first TFTs is an oxide semiconductor TFT. At least one second TFT among the plurality of second TFTs is covered with the organic insulating layer. The source and gate metal connection portion is not covered with the organic insulating layer.
    Type: Application
    Filed: August 4, 2017
    Publication date: October 31, 2019
    Inventors: Tetsuo KIKUCHI, Hajime IMAI, Takashi TERAUCHI, Shinya OHIRA, Isao OGASAWARA, Satoshi HORIUCHI