Abstract: The present invention relates to a carbonaceous material having a pore volume determined by performing Grand Canonical Monte Carlo simulation on an adsorption-desorption isotherm of carbon dioxide of 0.05 cm3/g or more and 0.20 cm3/g or less, and a ratio of desorption amount to adsorption amount (desorption amount/adsorption amount) at a relative pressure of 0.01 in the adsorption-desorption isotherm of 1.05 or more.

Abstract: A cutting tool comprises a substrate and a coating that coats the substrate, the coating including an ?-alumina layer provided on the substrate, the ?-alumina layer including crystal grains of ?-alumina, the ?-alumina layer including a lower portion and an upper portion, the upper portion being occupied in area at a ratio of 50% or more by crystal grains of ?-alumina having a (006) plane with a normal thereto having a direction within ±15° with respect to a direction of the normal to the second interface, the lower portion being occupied in area at a ratio of 50% or more by crystal grains of ?-alumina having a (006) plane with a normal thereto having a direction within ±15° with respect to the direction of the normal to the second interface, the ?-alumina layer having a thickness of 3 ?m or more and 20 ?m or less.

Abstract: A cutting tool including a rake face and a flank face includes: a substrate; and a coating film disposed on the substrate, wherein the coating film includes an Al2O3 layer, residual stress of the Al2O3 layer has a minimum value Rmin at at least a portion of a region d1 of the rake face, the minimum value Rmin is more than ?0.27 GPa and less than or equal to ?0.1 GPa.

Abstract: The present invention provides a delay locked loop (DLL) that can complete the process of adjusting the delay of an internal clock signal within a predetermined execution period. The DLL includes a DLL control circuit and a delay line circuit. The DLL control circuit sets the delay amount based on the phase difference between an input clock signal and an output clock signal. The delay line circuit performs a delay operation on the input clock signal according to the delay amount, thereby generating the output clock signal. The delay line circuit includes a plurality of delay units, each delay unit includes at least one delay element, and one of the delay units includes a greater number of delay elements than another delay unit.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A control circuit is provided herein, which can suppress the prolongation of a delay operation, so that the sequence using the DLL circuit to adjust the delay of the internal clock signal can be finished within a predetermined execution period. A control circuit includes a delay control unit delaying an input clock signal to generate an output clock signal based on the phase difference between the input clock signal and an output clock signal. The control circuit further includes a clock control unit. When the phase difference is greater than the first predetermined amount, the clock control unit inputs a clock signal delayed from the input clock signal by a second predetermined amount to the delay control unit as the input clock signal.

Abstract: A control circuit includes a control unit, a delay line unit, and a detection unit. The delay line unit delays an input clock signal based on the delay amount and generates an output clock signal. The detection unit performs a detection operation to detect the number of delayed clock cycles from the input clock signal to the output clock signal. The control unit changes the delay amount during a delay operation and controls the delay line unit so that the input clock signal is synchronized with the output clock signal. Before the delay operation, the detection unit performs the detection operation multiple times and detects a plurality of numbers of delayed clock cycles. The control unit sets the delay amount for the detection operation and sets the delay amount for the delay operation according to plurality of detected numbers of delayed clock cycles.

Abstract: A delay control circuit provided herein includes a DLL control circuit, a delay line circuit, and an N-value detection circuit. The DLL control circuit determines the delay amount based on the phase difference between the input and output clock signals. The delay line circuit delays the input clock signal based on the delay amount to generate an output clock signal. The N-value detection circuit performs an N-value detection operation for detecting the number of delayed clock cycles from the input clock signal to the output clock signal. When it is determined to be in an overflow state, the DLL control circuit outputs a signal indicating an overflow state to the N-value detection circuit. When the signal indicating the overflow state is received, the N-value detection circuit does not perform the N-value detection operation, but instead sets the number of delayed clock cycles to a predetermined value.

Abstract: Provided is a delay control circuit that can prevent an N-value detection sequence performed by the delay control circuit from exceeding a specific period. The delay control circuit includes: a DLL control circuit that sets a delay amount; a delay line circuit that performs a delay operation; and an N-value detection circuit that receives an input clock signal and an output clock signal and is configured to perform a pre-N-value detection operation. The pre-N-value detection operation includes detecting the number of delayed clock cycles from the input clock signal to the output clock signal as the number of pre-delayed clock cycles before a delay operation is performed. In response to that the number of pre-delayed clock cycles is not greater than a specific value, the DLL control circuit changes the delay amount so that the delay line circuit performs the delay operation in a fast mode.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A physiological signal processing apparatus for converting a physiological signal into sampling data having a predetermined frequency that is set according to the physiological signal includes an A/D converter and a computation unit. The A/D converter is configured to convert the physiological signal into high-speed sampling data by sampling the physiological signal at a frequency that is higher than the predetermined frequency. The computation unit is configured to convert the high-speed sampling data into sampling data having the predetermined frequency by setting time windows for the high-speed sampling data and calculating one representative value for each of the windows on the basis of high-speed sampling data in the window.

Abstract: A power supply device includes: a power supply circuit configured to supply power to a vital sensor; a capacitor electrically connected to the power supply circuit; a connector configured to supply power for charging the capacitor; and a shield case covering at least the power supply circuit and the capacitor to shield an electromagnetic wave.

Abstract: An electrolysis system includes at least one H2O electrolysis apparatus that electrolyzes water to produce hydrogen; and at least one CO2 electrolysis apparatus that electrolyzes carbon dioxide to produce carbon monoxide. The electrolysis system includes a co-electrolysis apparatus that co-electrolyzes water and carbon dioxide to produce less hydrogen per unit time than produced by the at least one H2O electrolysis apparatus and less carbon monoxide per unit time than produced by the at least one CO2 electrolysis apparatus.

Abstract: Provided is a carbon dioxide recovery system including: an absorption tower; a regeneration tower that takes in an absorbing solution that has absorbed carbon dioxide at the absorption tower, and separates the carbon dioxide from the absorbing solution using regenerated steam to regenerate the absorbing solution; first supply piping that supplies the absorbing solution regenerated in the regeneration tower to the absorption tower; a reclaimer that takes in part of the absorbing solution regenerated in the regeneration tower to remove degraded material and supplies the absorbing solution from which the degraded material has been removed to the regeneration tower or the first supply piping; an in-line viscometer that measures a viscosity of the absorbing solution flowing through the first supply piping; and a controller that controls an amount of the absorbing solution processed by the reclaimer based on the viscosity measured by the in-line viscometer.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A gas-liquid contact apparatus has a gas-liquid contact unit, a liquid supply system, and a gas supply system. The gas-liquid contact unit includes a plurality of stages which are allocated so as to be arranged in the lateral direction. Each of the plurality of stages includes a plurality of vertical flat plates arranged parallel to each other at intervals. The liquid supply system supplies a liquid to the gas-liquid contact unit, and causes the liquid to be circulated along the arrangement of the plurality of stages successively. The gas supply system supplies a gas to the gas-liquid contact unit, and causes the gas to be circulated along the arrangement of the plurality of stages successively. The supplied liquid flows down on the plurality of vertical flat plates in each of the plurality of stages, and comes into contact with the supplied gas.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.