Abstract: A power supply device includes: a power supply circuit configured to supply power to a vital sensor; a capacitor electrically connected to the power supply circuit; a connector configured to supply power for charging the capacitor; and a shield case covering at least the power supply circuit and the capacitor to shield an electromagnetic wave.

Abstract: An electrolysis system includes at least one H2O electrolysis apparatus that electrolyzes water to produce hydrogen; and at least one CO2 electrolysis apparatus that electrolyzes carbon dioxide to produce carbon monoxide. The electrolysis system includes a co-electrolysis apparatus that co-electrolyzes water and carbon dioxide to produce less hydrogen per unit time than produced by the at least one H2O electrolysis apparatus and less carbon monoxide per unit time than produced by the at least one CO2 electrolysis apparatus.

Abstract: Provided is a carbon dioxide recovery system including: an absorption tower; a regeneration tower that takes in an absorbing solution that has absorbed carbon dioxide at the absorption tower, and separates the carbon dioxide from the absorbing solution using regenerated steam to regenerate the absorbing solution; first supply piping that supplies the absorbing solution regenerated in the regeneration tower to the absorption tower; a reclaimer that takes in part of the absorbing solution regenerated in the regeneration tower to remove degraded material and supplies the absorbing solution from which the degraded material has been removed to the regeneration tower or the first supply piping; an in-line viscometer that measures a viscosity of the absorbing solution flowing through the first supply piping; and a controller that controls an amount of the absorbing solution processed by the reclaimer based on the viscosity measured by the in-line viscometer.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A gas-liquid contact apparatus has a gas-liquid contact unit, a liquid supply system, and a gas supply system. The gas-liquid contact unit includes a plurality of stages which are allocated so as to be arranged in the lateral direction. Each of the plurality of stages includes a plurality of vertical flat plates arranged parallel to each other at intervals. The liquid supply system supplies a liquid to the gas-liquid contact unit, and causes the liquid to be circulated along the arrangement of the plurality of stages successively. The gas supply system supplies a gas to the gas-liquid contact unit, and causes the gas to be circulated along the arrangement of the plurality of stages successively. The supplied liquid flows down on the plurality of vertical flat plates in each of the plurality of stages, and comes into contact with the supplied gas.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: A memory device and a refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area near the plurality of normal areas. The redundancy area includes a plurality of redundancy word lines. A plurality of boundary word lines are arranged near boundaries between the plurality of normal areas and the redundancy area. The controller refreshes the plurality of redundancy word lines in sequence, and refreshes the plurality of boundary word lines in sequence after refreshing the plurality of redundancy word lines in sequence.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A DLL device and an operation method for the DLL device are provided. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line delays an input clock in response to a delay code to provide a delayed clock. The replica circuit generates a feedback clock according to the delayed clock. The phase detector compares the input clock with the feedback clock to generate a delay control signal. The delay controller generates the delay code at a first time point according to the delay control signal based on a control clock and delays a replica delay time length to provide the delay code to the delay line at a second time point. The delay line adjusts the input clock at the second time point. A cycle of the control clock is adjusted to be larger than the replica delay time length.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.

Abstract: A memory device and a row-hammer refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area adjacent to the plurality of normal areas. The redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged. The controller is configured to row-hammer refresh the plurality of normal areas without row-hammer refreshing the redundancy area.

Abstract: A memory device and a refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area near the plurality of normal areas. The redundancy area includes a plurality of redundancy word lines. A plurality of boundary word lines are arranged near boundaries between the plurality of normal areas and the redundancy area. The controller refreshes the plurality of redundancy word lines in sequence, and refreshes the plurality of boundary word lines in sequence after refreshing the plurality of redundancy word lines in sequence.

Abstract: A memory device and a row-hammer refresh method thereof are provided. The memory device includes a memory array and a controller. The memory array includes a plurality of normal areas and a redundancy area adjacent to the plurality of normal areas. The redundancy area includes a plurality of first word lines and a plurality of second word lines which are alternately arranged. The controller is configured to row-hammer refresh the plurality of normal areas without row-hammer refreshing the redundancy area.

Abstract: A gas-liquid contact apparatus has a gas-liquid contact unit, a liquid supply system, and a gas supply system. The gas-liquid contact unit includes a plurality of stages which are allocated so as to be arranged in the lateral direction. Each of the plurality of stages includes a plurality of vertical flat plates arranged parallel to each other at intervals. The liquid supply system supplies a liquid to the gas-liquid contact unit, and causes the liquid to be circulated along the arrangement of the plurality of stages successively. The gas supply system supplies a gas to the gas-liquid contact unit, and causes the gas to be circulated along the arrangement of the plurality of stages successively. The supplied liquid flows down on the plurality of vertical flat plates in each of the plurality of stages, and comes into contact with the supplied gas.

Abstract: A delay locked loop device (DLL) and an update method therefor are provided. The DLL device includes a DLL and an update circuit. The DLL is enabled according to an enable signal, thereby delaying an input clock to provide a delayed clock. The update circuit includes a flag generating circuit and an enable circuit. The flag generating circuit provides an update flag based on a default time interval. The enable circuit triggers the enable signal to a first logic level according to the update flag, and transitions the enable signal from the first logic level to a second logic level before the end of the default time interval. The default time interval is shorter than the refresh cycle of the memory.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO receives data from the memory circuit and outputs data synchronously with a first clock signal. The second FIFO receives data output from the first FIFO and outputs data synchronously with the first clock signal. The input/output circuit outputs data output from the second FIFO. The second FIFO is disposed in the vicinity of the input/output circuit than the first FIFO.