Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a first complementary inverter configured to receive a carry in signal, a second complementary inverter having an input coupled to the first complementary inverter and having an output at which a carry out signal is produced, and an output buffer subcircuit coupled to the input of the second complementary inverter. The output buffer subcircuit can include a first output buffer transistor coupled in series with a second output buffer transistor. The first complementary inverter can receive the carry in signal through a transmission gate that is controlled by two shift register clock signals.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.

Abstract: A display may include an array of pixels. A pixel can include an organic light-emitting diode, up to three thin-film transistors, and up to two capacitors. The pixel can include a drive transistor, an emission transistor, and a select transistor. The select transistor can be used to apply a reference voltage to the gate of the drive transistor during a global reset phase and during a global threshold voltage sampling phase and can also be used to apply a data voltage to the gate of the drive transistor during a data programming phase. The drive transistor can receive a power supply voltage that toggles between a low voltage during the global reset phase and a high voltage during other phases of operation. Configured and operated in this way, the pixel need not include separate dedicated anode reset and initialization transistors.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a first complementary inverter configured to receive a carry in signal, a second complementary inverter having an input coupled to the first complementary inverter and having an output at which a carry out signal is produced, and an output buffer subcircuit coupled to the input of the second complementary inverter. The output buffer subcircuit can include a first output buffer transistor coupled in series with a second output buffer transistor. The first complementary inverter can receive the carry in signal through a transmission gate that is controlled by two shift register clock signals.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: An electronic device may include display and touch circuitry. The circuitry may include an array of pixels. Each pixel in the array may include at least a light-emitting diode, a drive transistor coupled in series with the light-emitting diode, a storage capacitor coupled to a gate terminal of the drive transistor, and an anode reset transistor configured to reset an anode of the light-emitting diode and coupled to an anode reset voltage line. The light-emitting diode may have a cathode that is capacitively coupled to one or more touch sensor electrodes. The anode reset transistor may be activated while the touch sensor electrodes are performing touch sensing operations during a vertical blanking period. The cathode can be formed from a cathode layer driven to a ground voltage and disconnected from one or more electrically floating cathode layer portions elevated relative to the cathode layer by floating cathode support structures.

Abstract: A display may include organic light-emitting diode (OLED) pixels. Each pixel may include OLED layers that are interposed between an anode and a cathode. The anode may be formed on a substrate. A layer of material that defines a plurality of bumps or recesses may be formed on the substrate. The anode may conform to the layer of material and may have a plurality of curved portions that are aligned with the bumps or recesses. The anode may have a side mirror portion that conforms to a tapered surface. A black pixel definition layer may be positioned above or below the side mirror portion of the anode. A pixel may include a pixel definition layer that defines multiple light-emitting apertures that overlap a single anode. The multiple light-emitting apertures may have circular, square, or non-square rectangular footprints.

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

Abstract: A display may include an array of pixels. Each pixel in the array may include a light-emitting diode having an anode terminal coupled to a first power supply terminal configured to receive a positive power supply voltage and having a cathode terminal coupled to a second power supply terminal configured to receive a ground power supply voltage. The display can further include a gate driver circuit configured to output a control signal to a row of display pixels in the array. The control signal can be driven between the positive power supply voltage and a low voltage different than the ground power supply voltage.

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

Abstract: An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels, that include hybrid thin-film transistor structures formed using semiconducting-oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. A drive transistor in the display pixel may be a top-gate semiconducting-oxide thin-film transistor and a switching transistor in the display pixel may be a top-gate silicon thin-film transistor. A storage capacitor in the display may include a conductive semiconducting-oxide electrode.