Patents by Inventor Shinya Sadohara

Shinya Sadohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11427260
    Abstract: A reinforcement is formed into an elongated shape, and includes a reinforcement body in which a housing part opened toward an outer peripheral side is formed and a covering part attached to close an opening of the housing part. A module component which is an electrical component or a wiring component may be housed in the reinforcement while being attached to the covering part.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 30, 2022
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji Yamaguchi, Housei Mizuno, Shinya Sadohara, Hiroki Hirai, Shinya Itou
  • Patent number: 11257609
    Abstract: A wire harness includes an electrical wire, a sheet material welded to an insulating covering of the electrical wire disposed on a main surface, and a cover fixed to the sheet material. The cover covers at least part of the electrical wire disposed on the sheet material along a longitudinal direction of the electrical wire from an opposite side of the electrical wire from the sheet material.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 22, 2022
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Housei Mizuno, Daichi Fukushima, Miyu Aramaki, Shinya Sadohara, Ryuta Takakura, Tetsuya Nishimura
  • Patent number: 11208058
    Abstract: An electrical component-attached wire harness includes a base material disposed in a vehicle, a wire harness disposed along the base material, and at least one electrical component to which an end portion of the wire harness is connected. For example, the at least one electrical component may include an electronic control unit.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 28, 2021
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji Yamaguchi, Housei Mizuno, Shinya Sadohara, Hiroki Hirai, Shinya Itou, Yutaka Matsumura
  • Publication number: 20210020331
    Abstract: A wire harness includes an electrical wire, a sheet material welded to an insulating covering of the electrical wire disposed on a main surface, and a cover fixed to the sheet material. The cover covers at least part of the electrical wire disposed on the sheet material along a longitudinal direction of the electrical wire from an opposite side of the electrical wire from the sheet material.
    Type: Application
    Filed: March 26, 2019
    Publication date: January 21, 2021
    Applicants: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Housei MIZUNO, Daichi FUKUSHIMA, Miyu ARAMAKI, Shinya SADOHARA, Ryuta TAKAKURA, Tetsuya NISHIMURA
  • Patent number: 10819094
    Abstract: A protector made of a hollow plate material is externally fitted to an electric wire arranged at a position at which a load is exerted. A protector-equipped electric wire is provided with an electric wire arranged at a position at which a load is exerted, and a protector externally fitted to the electric wire. The protector is made of a folded hollow plate material, the hollow plate material including a plurality of plate-shaped portions, and interposed portions that are arranged extending in one direction between the plurality of plate-shaped portions and form hollow spaces between the plurality of plate-shaped portions, the protector including a plurality of wall portions that covers the electric wire. The plurality of wall portions including at least one load bearing wall portion that is arranged so that the direction in which the interposed portions extend corresponds to a direction in which the load is exerted.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: October 27, 2020
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Housei Mizuno, Yasuyuki Yamamoto, Shinya Sadohara, Kousei Nogami, Makoto Iwata
  • Publication number: 20200180525
    Abstract: An electrical component-attached wire harness is configured to be able to be assembled to a vehicle. The electrical component-attached wire harness includes a base material disposed in a vehicle, a wire harness disposed along the base material, and at least one electrical component to which an end portion of the wire harness is connected.
    Type: Application
    Filed: June 26, 2018
    Publication date: June 11, 2020
    Applicants: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji YAMAGUCHI, Housei MIZUNO, Shinya SADOHARA, Hiroki HIRAI, Shinya ITOU, Yutaka MATSUMURA
  • Publication number: 20200164924
    Abstract: A reinforcement is formed into an elongated shape, and includes a reinforcement body in which a housing part opened toward an outer peripheral side is formed and a covering part attached to close an opening of the housing part. A module component which is an electrical component or a wiring component may be housed in the reinforcement while being attached to the covering part.
    Type: Application
    Filed: June 29, 2018
    Publication date: May 28, 2020
    Applicants: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Koji YAMAGUCHI, Housei MIZUNO, Shinya SADOHARA, Hiroki HIRAI, Shinya ITOU
  • Patent number: 10214160
    Abstract: A wire module includes multiple wires and a wire protection member including a supporting plate portion with a main surface on which the multiple wires can be arranged. A partitioning portion that partitions the plurality of wires in a width direction of the supporting plate portion is formed due to the supporting plate portion being partially cut and raised. A partitioning plate portion includes a first partitioning portion and a second partitioning portion that are cut and raised from mutually opposite sides in the width direction of the supporting plate portion and come into contact with each other in directions of supporting each other in their upright states, in a state of being mutually upright.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: February 26, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Housei Mizuno, Yasuyuki Yamamoto, Shinya Sadohara
  • Publication number: 20190036311
    Abstract: A protector made of a hollow plate material is externally fitted to an electric wire arranged at a position at which a load is exerted. A protector-equipped electric wire is provided with an electric wire arranged at a position at which a load is exerted, and a protector externally fitted to the electric wire. The protector is made of a folded hollow plate material, the hollow plate material including a plurality of plate-shaped portions, and interposed portions that are arranged extending in one direction between the plurality of plate-shaped portions and form hollow spaces between the plurality of plate-shaped portions, the protector including a plurality of wall portions that covers the electric wire. The plurality of wall portions including at least one load bearing wall portion that is arranged so that the direction in which the interposed portions extend corresponds to a direction in which the load is exerted.
    Type: Application
    Filed: January 23, 2017
    Publication date: January 31, 2019
    Applicants: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Housei MIZUNO, Yasuyuki YAMAMOTO, Shinya SADOHARA, Kousei NOGAMI, Makoto IWATA
  • Publication number: 20180170287
    Abstract: A wire module includes multiple wires and a wire protection member including a supporting plate portion with a main surface on which the multiple wires can be arranged. A partitioning portion that partitions the plurality of wires in a width direction of the supporting plate portion is formed due to the supporting plate portion being partially cut and raised. A partitioning plate portion includes a first partitioning portion and a second partitioning portion that are cut and raised from mutually opposite sides in the width direction of the supporting plate portion and come into contact with each other in directions of supporting each other in their upright states, in a state of being mutually upright.
    Type: Application
    Filed: June 2, 2016
    Publication date: June 21, 2018
    Inventors: Housei MIZUNO, Yasuyuki YAMAMOTO, Shinya SADOHARA
  • Patent number: 8853103
    Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 7, 2014
    Assignee: Sumco Techxiv Corporation
    Inventor: Shinya Sadohara
  • Publication number: 20130295780
    Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.
    Type: Application
    Filed: March 15, 2013
    Publication date: November 7, 2013
    Inventor: Shinya SADOHARA
  • Patent number: 8573969
    Abstract: A silicon wafer preferable to a semiconductor device is produced by determining a heat treatment condition hardly causing slip dislocations and heat-treating the silicon wafer under the condition. The resistance is calculated by using a calculation formula used for predicting the slip resistance of the wafer from the density, size, and residual solid-solution oxygen concentration of the oxygen precipitation in the silicon wafer, the state of oxygen precipitation such that heat treatment not causing any slip dislocation can be carried out is designed, and thus a silicon wafer heat treatment method under the heat treatment condition not causing any slip dislocation is determined. A silicon wafer heat-treated under such a condition can be provided.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 5, 2013
    Assignee: Sumco TechXIV Corporation
    Inventors: Shinya Sadohara, Kozo Nakamura, Shiro Yoshino
  • Patent number: 8426297
    Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: April 23, 2013
    Assignee: Sumco Techxiv Corporation
    Inventor: Shinya Sadohara
  • Publication number: 20130095660
    Abstract: To final polish a finish-polished surface using a final polishing solution whose chief component is a weakly basic aqueous solution that does not contain abrasive grains. During the final polishing, the weakly basic aqueous solution having an alkali concentration that reduces a haze value of a final-polished surface below the haze value of the finish-polished surface of the wafer is used as the chief component of the final polishing solution.
    Type: Application
    Filed: July 1, 2011
    Publication date: April 18, 2013
    Applicant: SUMCO CORPORATION
    Inventors: Ryuichi Tanimoto, Shinya Sadohara, Takeru Takushima
  • Publication number: 20110143526
    Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.
    Type: Application
    Filed: August 7, 2009
    Publication date: June 16, 2011
    Applicant: SUMCO TECHXIV CORPORATION
    Inventor: Shinya Sadohara
  • Patent number: 7875116
    Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: January 25, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
  • Patent number: 7759227
    Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: July 20, 2010
    Assignee: Sumco Techxiv Corporation
    Inventors: Susumu Maeda, Takahisa Sugiman, Shinya Sadohara, Shiro Yoshino, Kouzo Nakamura
  • Publication number: 20100075267
    Abstract: A silicon wafer preferable to a semiconductor device is produced by determining a heat treatment condition hardly causing slip dislocations and heat-treating the silicon wafer under the condition. The resistance is calculated by using a calculation formula used for predicting the slip resistance of the wafer from the density, size, and residual solid-solution oxygen concentration of the oxygen precipitation in the silicon wafer, the state of oxygen precipitation such that heat treatment not causing any slip dislocation can be carried out is designed, and thus a silicon wafer heat treatment method under the heat treatment condition not causing any slip dislocation is determined. A silicon wafer heat-treated under such a condition can be provided.
    Type: Application
    Filed: September 28, 2007
    Publication date: March 25, 2010
    Inventors: Shinya Sadohara, Kozo Nakamura, Shiro Yoshino
  • Publication number: 20090061140
    Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.
    Type: Application
    Filed: February 14, 2006
    Publication date: March 5, 2009
    Applicant: SUMCO TECHXIV KABUSHIKI KAISHA
    Inventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka