Patents by Inventor Shinya Soeda
Shinya Soeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6822279Abstract: A semiconductor device has a semiconductor substrate and a resistor group and/or a signal interconnection layer in a region of the semiconductor substrate. A shielding layer is located above and/or below the region where the resistor group and/or the signal interconnection layer are located.Type: GrantFiled: February 20, 2002Date of Patent: November 23, 2004Assignee: Renesas Technology Corp.Inventor: Shinya Soeda
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Publication number: 20040108553Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.Type: ApplicationFiled: December 3, 2003Publication date: June 10, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroyasu Nohsoh, Shinya Soeda
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Patent number: 6680539Abstract: Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns 96 and 98 having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions 94 are extracted followed by as many smaller free regions 97 as possible. The dummy patterns 98 are laid out in the extracted free regions.Type: GrantFiled: April 25, 2000Date of Patent: January 20, 2004Assignee: Renesas Technology Corp.Inventors: Hiroyasu Nohsoh, Hiroki Shinkawata, Shinya Soeda
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Patent number: 6670680Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.Type: GrantFiled: May 1, 2001Date of Patent: December 30, 2003Assignee: Renesas Technology Corp.Inventors: Hiroyasu Nohsoh, Shinya Soeda
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Patent number: 6607964Abstract: A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is removed to form a first opening in the first silicide protection film, an N+ diffusion layer is formed in a portion of the silicon substrate exposed from the first opening, the first resist pattern is removed, and a metallic film is deposited to form a first silicide layer on the N+ diffusion layer according to a silicide process.Type: GrantFiled: June 6, 2001Date of Patent: August 19, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hidenori Sato, Shinya Soeda
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Publication number: 20030052352Abstract: A semiconductor device has a semiconductor substrate and a resistor group and/or a signal interconnection layer on a region in this semiconductor substrate. A shielding layer provided above and/or below the region where the resistor group and/or the signal interconnection layer has been provided.Type: ApplicationFiled: February 20, 2002Publication date: March 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Shinya Soeda
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Publication number: 20020195712Abstract: Patterns to be included in a multi-layer wiring structure of a semiconductor device are designed layer by layer. Functional patterns 92 necessary for implementing functions of the semiconductor device are formed first. A plurality of types of dummy patterns 96 and 98 having different sizes are then designed in free regions not occupied by the functional patterns. While the dummy patterns are being designed, the largest possible number of free regions 94 are extracted followed by as many smaller free regions 97 as possible. The dummy patterns 98 are laid out in the extracted free regions.Type: ApplicationFiled: April 25, 2000Publication date: December 26, 2002Inventors: Hiroyasu Nohsoh, Hiroki Shinkawata, Shinya Soeda
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Publication number: 20020106855Abstract: A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is removed to form a first opening in the first silicide protection film, an N+ diffusion layer is formed in a portion of the silicon substrate exposed from the first opening, the first resist pattern is removed, and a metallic film is deposited to form a first silicide layer on the N+ diffusion layer according to a silicide process.Type: ApplicationFiled: June 6, 2001Publication date: August 8, 2002Inventors: Hidenori Sato, Shinya Soeda
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Publication number: 20020093051Abstract: A dual gate type CMOS device according to the present invention includes a silicon substrate having a trench in the main surface and a gate electrode including a polysilicon film and a tungsten silicide film formed above the main surface via a gate insulating film. The polysilicon film has a first part into which p type impurities are doped, a second part into which n type impurities are doped and a connection part which connects the first part and the second part within the trench, and part of the tungsten silicide film located above the connection part is removed.Type: ApplicationFiled: May 1, 2001Publication date: July 18, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hiroyasu Nohsoh, Shinya Soeda
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Patent number: 6388295Abstract: The semiconductor device has a triple well structure. The triple well and other wells have impurity concentration distributions in the depth direction, which are determined in accordance with required function. Thereby, the required performances such as suppression of a leak current can be achieved even in a miniaturized structure.Type: GrantFiled: September 18, 2000Date of Patent: May 14, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomohiro Yamashita, Yoshinori Okumura, Atsushi Hachisuka, Shinya Soeda
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Patent number: 6355387Abstract: A technique of correcting a mask pattern without alleviating the design rule or measuring all contact hole diameters. Undulations are inspected in a region for forming contact holes (step S3). On the basis of the surface shape (undulations) determined at step S3, the contact hole diameter is predicted in the case of use of the mask hole diameter fabricated at step S1 (step S4). On the basis of the result of prediction, the mask pattern M is corrected to mask patter M′ according to the mask hole diameter (step S5).Type: GrantFiled: November 22, 1995Date of Patent: March 12, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masato Fujinaga, Shinya Soeda
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Patent number: 6331462Abstract: A semiconductor substrate is arranged to have a DRAM area in which to form at a high density gate electrodes of transistors serving as DRAM components, and a peripheral circuit area in which to form at a relatively low density gate electrodes of transistors as peripheral circuit components. A resist film is formed in corresponding relation to the gate electrodes of the DRAM. After an insulating film is etched, a resist film is formed in corresponding relation to the gate electrodes of the peripheral circuits. A conductive layer is then etched while the resist film and insulating film left in the DRAM area are being used as masks, whereby the gate electrodes are formed in the DRAM area and peripheral circuit area.Type: GrantFiled: December 3, 1999Date of Patent: December 18, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tatsuo Kasaoka, Atsushi Hachisuka, Shinya Soeda
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Patent number: 6323560Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.Type: GrantFiled: January 27, 2000Date of Patent: November 27, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
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Patent number: 6218235Abstract: A method of manufacturing a semiconductor device having a memory device and a logic device on the same semiconductor substrate is provided without reducing reliability of the semiconductor device and making a manufacturing process unnecessarily complicated. A silicon oxide film which serves as a salicide protection film in the logic device formation region is subjected to wet isotropic etching. The process completely removes the silicon oxide film in the memory device formation region. Thus, the silicon oxide film is left only in a prescribed portion in the logic device formation region. As a result, the silicon oxide film is not left on an inner wall of a recess formed by a silicon nitride film between gate electrodes. Consequently, a good self alignment contact opening is formed toward a source/drain region in the memory device formation region.Type: GrantFiled: April 4, 2000Date of Patent: April 17, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Atsushi Hachisuka, Hiroyasu Nohsoh, Shinya Soeda
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Patent number: 6068952Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.Type: GrantFiled: January 15, 1999Date of Patent: May 30, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
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Patent number: 5892291Abstract: The present invention includes a first semiconductor element forming member formed in a first layer, a first measurement mark formed by the same manufacturing step as the first semiconductor element forming member, a second semiconductor element forming member formed in a second layer above the first layer, and a second measurement mark formed in the same manufacturing step as the second semiconductor element forming member for measuring registration accuracy between the first and second semiconductor element forming members. The first measurement mark has a pattern which receives same influence of aberration as the first semiconductor element forming member when irradiated with light, and the second measurement mark has a pattern which receives same influence of aberration as the second semiconductor element forming member when irradiated with light. Thus, a registration accuracy measurement mark taking into consideration the influence of aberration can be provided.Type: GrantFiled: June 27, 1996Date of Patent: April 6, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Koichiro Narimatsu, Shigenori Yamashita, Nobuyuki Yoshioka, Shinya Soeda, Atsushi Hachisuka, Koji Taniguchi, Yuki Miyamoto, Takayuki Saito, Ayumi Minamide
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Patent number: 5329146Abstract: In a memory cell formed of one transistor and one capacitor, the capacitor includes a stacked type capacitor region extending over the gate electrode and word line of the transfer gate transistor, and a trench type capacitor region extending into a groove part formed in the field isolation film for element separation. The trench type capacitor region is formed between a pair of word lines extending on the field isolation film. Each storage node of adjacent capacitors is isolated on the bottom surface of the groove.Type: GrantFiled: August 24, 1992Date of Patent: July 12, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shinya Soeda