Abstract: A semiconductor device includes a capacitance adjusting region. The capacitance adjusting region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of control trench gates. The first semiconductor layer is provided as a surface layer at an upper surface of the semiconductor substrate. The second semiconductor layer is selectively provided at an upper surface of the first semiconductor layer. The second semiconductor layer contacts a side surface of each of the control trench gates. The first semiconductor layer and the second semiconductor layer are electrically connected to an emitter electrode of a transistor. A control trench electrode of at least one control trench gate is electrically connected to a gate electrode of the transistor.

Abstract: To provide a semiconductor device that includes: a semiconductor substrate provided with a semiconductor portion that is at least one of a gate insulating film, a pn junction, or a drift layer of a terminal region; an insulating film provided on the semiconductor portion; a metal electrode having an opening that overlaps the semiconductor portion in plan view and is provided on a side opposite to the semiconductor portion with respect to the insulating film in cross-sectional view; and a plated electrode provided at at least a portion of an inside of the opening using the metal electrode as a material to be plated.

Abstract: A semiconductor device includes: a first control electrode and a second control electrode for switching that are formed in a first main surface and a second main surface, respectively, of a semiconductor substrate; a first control electrode pad electrically connected to the first control electrode; a first through-via penetrating the semiconductor substrate in a thickness direction and including a conductor electrically connecting the first main surface to the second main surface; and a second control electrode pad formed on the first main surface and electrically connected to the second control electrode through the first through-via.

Abstract: A semiconductor device includes a capacitance adjusting region. The capacitance adjusting region includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a plurality of control trench gates. The first semiconductor layer is provided as a surface layer at an upper surface of the semiconductor substrate. The second semiconductor layer is selectively provided at an upper surface of the first semiconductor layer. The second semiconductor layer contacts a side surface of each of the control trench gates. The first semiconductor layer and the second semiconductor layer are electrically connected to an emitter electrode of a transistor. A control trench electrode of at least one control trench gate is electrically connected to a gate electrode of the transistor.

Abstract: A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.

Abstract: In a mesa region sandwiched between adjacent active trenches among mesa regions that are regions each sandwiched between adjacent trenches, a third semiconductor layer has regions discretely arranged in a first direction so as to be in contact with one active trench of the adjacent active trenches and not in contact with the other active trench, and regions discretely arranged in the first direction so as to be in contact with the other active trench and not in contact with the one active trench. In the mesa region sandwiched between the adjacent active trenches, a fourth semiconductor layer is disposed between the third semiconductor layer on the side in contact with the one active trench and the third semiconductor layer on the side in contact with the other active trench in plan view and between the respective regions of the third semiconductor layer discrete in the first direction.

Abstract: A semiconductor device includes: a channel stopper region of a first conductivity type formed on a surface layer of a drift layer in a termination region; a first termination trench formed in the drift layer in the termination region; a plurality of termination electrodes provided in the first termination trench while being surrounded by a first termination insulating film; and a channel stopper electrode provided on an upper surface of the drift layer while being electrically connected to the channel stopper region and the termination electrodes, wherein the plurality of termination electrodes include a first termination electrode and a second termination electrode.

Abstract: An object is to provide a technology that can suppress a decrease in the saturated current while reducing the amount of gate charge. A semiconductor device includes a semiconductor substrate with a drift layer, a carrier storage layer, and a base layer, and a two-stage active trench structure in the semiconductor substrate. A thickness of a lower-stage insulating film in contact with a side portion of a lower stage electrode is greater than a thickness of an upper-stage insulating film in contact with a side portion of an upper stage electrode, at least one of conditions (a), (b), or (c) is satisfied, and a lower end of the upper stage electrode is located above a position at which an integrated value of impurity concentrations of the carrier storage layer in a vertical direction is halved.

Abstract: According to the disclosure, a semiconductor device includes a semiconductor substrate including an IGBT region and a diode region, a first electrode provided on an upper surface of the semiconductor substrate and a second electrode provided on a back surface of the semiconductor substrate, wherein the diode region includes an n-type drift layer, a p-type anode layer provided on an upper surface side of the drift layer, and an n-type cathode layer provided on a back surface side of the drift layer, a lifetime control region having crystal defect density higher than crystal defect density of other portions of the drift layer and including protons is provided on a back surface side relative to a center in a thickness direction of the semiconductor substrate among the drift layer, and a maximum value of donor concentration of the lifetime control region is equal to or less than 1.0×1015/cm3.

Abstract: To provide a semiconductor device that includes: a semiconductor substrate provided with a semiconductor portion that is at least one of a gate insulating film, a pn junction, or a drift layer of a terminal region; an insulating film provided on the semiconductor portion; a metal electrode having an opening that overlaps the semiconductor portion in plan view and is provided on a side opposite to the semiconductor portion with respect to the insulating film in cross-sectional view; and a plated electrode provided at at least a portion of an inside of the opening using the metal electrode as a material to be plated.

Abstract: A semiconductor device includes an emitter electrode, a temperature sensing unit provided adjacent to the emitter electrode, a sense wiring, and a first wire bond portion provided adjacent to a connection portion between the emitter electrode and the sense wiring. The sense wiring includes a first sense wiring portion, a second sense wiring portion, and a bent portion. A distance from the connection portion to the first wire bond portion is shorter than a distance from the bent portion to the connection portion.

Abstract: A semiconductor device according to the present disclosure is an insulated gate bipolar transistor (IGBT) including: a semiconductor substrate; a two-stage active trench having an upper electrode connected to a gate electrode and covered with an upper insulating film in an upper stage, a lower electrode connected to the gate electrode and covered with a lower insulating film in a lower stage, and a boundary insulating film located between the upper electrode and the lower electrode inside a trench provided on a front surface side of the semiconductor substrate; and a dummy trench having a dummy electrode covered with a dummy insulating film inside a trench provided on the front surface side of the semiconductor substrate, wherein a film thickness of the lower insulating film and a film thickness of the dummy insulating film are thicker than a film thickness of the upper insulating film.

Abstract: A semiconductor device has an alternating region in which insulated gate bipolar transistor (IGBT) regions and diode regions are alternately arranged linearly in a plan view. In the alternating region, a width, in the first direction, of an IGBT region closest to the center of a cell region is equal to or smaller than widths of other IGBT regions in the first direction, and a width, in the first direction, of a diode region closest to a center of the cell region is equal to or smaller than widths of other diode regions in the first direction.

Abstract: Even if there is a change in the shape of a transfer mold power module is required, a change in a position of the electrode of the module is facilitated by separating electrode terminals of a power module from the electrodes and retrofitting the separated electrode terminals to the electrodes with high precision. A semiconductor device includes a mold resin enclosing a semiconductor chip, an electrode electrically connected to the semiconductor chip and exposed in an opening provided in the mold resin, and an electrode terminal having a contact portion that covers the electrode and is in electrical contact with the electrode, a plurality of projections formed to surround the contact portion and provided between a side surface of the opening and the contact portion, a contact end portion having the contact portion and an open end portion which is a different end portion from the contact end portion.

Abstract: A semiconductor device includes a plurality of trenches formed on a first main surface of a semiconductor substrate, and insulating films and electrodes formed in the plurality of trenches. The plurality of trenches include a first trench and a second trench deeper than the first trench and wider than the first trench. A bottom layer of a second conductivity type, in contact with a bottom of the second trench and not in contact with the first trench, is disposed under the second trench.

Abstract: In plan view of an RC-IGBT, a boundary region has an occupancy rate of an n+-type source layer per unit area, the occupancy rate being smaller than an occupancy rate of the n+-type source layer per unit area in an IGBT region, and the boundary region has an occupancy rate of a p+-type contact layer per unit area, the occupancy rate being smaller than an occupancy rate of the p+-type contact layer per unit area in an IGBT region.

Abstract: A semiconductor device according to the present disclosure includes a dummy active trench including an upper electrode and a lower electrode. The upper electrode is connected to the gate electrode or to the emitter electrode, or at a floating potential. The lower electrode is connected to the gate electrode or to the emitter electrode, or at a floating potential. The dummy active trench includes an upper insulating film formed on a side surface of the upper electrode, a lower insulating film formed on a side surface of the lower electrode, and a boundary insulating film formed between the upper electrode and the lower electrode. The thickness of the upper insulating film in a right-left direction is larger than the thickness of the lower insulating film in the right-left direction. In a sectional view, the area of the upper electrode is smaller than the area of the lower electrode.

Abstract: When a positive gate voltage is applied to a first one of a first gate electrode and a second gate electrode, and current flows from a collector electrode to an emitter electrode, a semiconductor device applies a positive gate voltage to a second one of the first gate electrode and the second gate electrode. When a positive gate voltage is applied to the first one and current flows from the emitter electrode to the collector electrode, the semiconductor device applies voltage equal to or less than reference voltage to the second one.

Abstract: A semiconductor device includes a source layer of a first conductivity type located in a surface portion of a semiconductor layer and defined by a concentration profile of a first impurity, a base layer of a second conductivity type located on a lower side of the source layer and defined by a concentration profile of a second impurity, a carrier stored layer of the first conductivity type located on a lower side of the base layer and defined by a concentration profile of a third impurity, a drift layer of the first conductivity type located on a lower side of the carrier stored layer, and a CSC layer of the second conductivity type defined by a concentration profile of a fourth impurity. A region containing the fourth impurity includes a region where a region containing the second impurity and a region containing the third impurity overlap each other.

Abstract: First and second surface electrodes are disposed so as to sandwich finger wiring extending in a first direction. A gate electrode extends in a second direction. A third surface electrode connects the first surface electrode and the second surface electrode between a tip of the finger wiring and gate wiring. A finger wiring extension portion extends from the tip of the finger wiring toward the gate wiring while avoiding the third surface electrode. A gate electrode crossing the third surface electrode in plan view is electrically connected to the finger wiring extension portion.