Abstract: A first buffer layer and a second buffer layer of a first conductivity type have a higher impurity concentration than a drift layer of the first conductivity type. The first buffer layer is provided in the drift layer. The second buffer layer is provided between a second main surface and the first buffer layer. A separation distance is provided between a location where the first buffer layer has a peak impurity concentration and a location where the second buffer layer has a peak impurity concentration in a thickness direction. The location where the first buffer layer has the peak impurity concentration in the thickness direction has a distribution portion and a non-distribution portion in a plan layout. The non-distribution portion has an effective width smaller than the separation distance. The effective width is twice a farthest distance from the distribution portion in the non-distribution portion in the plan layout.

Abstract: An interconnection member has a bonded surface in contact with a bonding member. In plan view seen in a direction perpendicular to a front surface electrode, the bonded surface covers at least a portion of each of a plurality of diode regions. The plurality of diode regions include a first diode region, a second diode region, and a third diode region. In plan view, the second diode region is located in a first direction with respect to the first diode region and is spaced from the first diode region. In plan view, the third diode region is located in a second direction, which is perpendicular to the first direction, with respect to the first diode region, and is spaced from each of the first diode region and the second diode region.

Abstract: In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.

Abstract: A semiconductor device includes a transistor and a diode formed at a common semiconductor substrate. The diode region includes: a fifth semiconductor layer of a second conductivity type; a second semiconductor layer of the second conductivity type provided on the fifth semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to a first main surface of the semiconductor substrate; a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer; and a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from a second main surface.

Abstract: A semiconductor device includes a first contact layer connected to a lower portion of a first trench contact portion and a second contact layer connected to a lower portion of a second trench contact portion. The distance between a first side portion of a first trench and the first trench contact portion is larger than that between a second side portion of the first trench and the second trench contact portion in a plan view, and the first contact layer is separated from the first side portion and the second contact layer is connected to the second side portion in a cross section. With this structure, it is possible to provide a technique for achieving an appropriate channel region.

Abstract: Prevented is local increase of a temperature of a chip in a semiconductor device including a diode region and an IGBT region. A semiconductor device includes a chip of an RC-IGBT including an IGBT region functioning as an IGBT and a plurality of diode regions functioning as a diode. The plurality of diode regions are disposed to form an island-like shape in an effective region which is a region made up of the IGBT region and the diode regions. When a length of one side of one of the diode regions is WD, an interval of the diode regions adjacent to each other is WI, a length of one side of the effective region is WC, and a thickness of the chip is t, satisfied are relationships of 2t<WD<5t, 2t<WI<5t, and WD+WI<WC/6.

Abstract: All of four of built-in gate resistance trenches function as practical built-in gate resistance trenches. A first end portion of each of four of the built-in gate resistance trenches is electrically connected to a wiring side contact region of a gate wiring via a wiring contact. A second end portion of each of four of the built-in gate resistance trenches is electrically connected to a pad side contact region of a gate pad via a pad contact. In each of four of the built-in gate resistance trenches, a distance between the wiring contact and the pad contact is defined as an inter-contact distance.

Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.

Abstract: An RC-IGBT includes a semiconductor substrate having a cell region, a wiring region, and a termination region. The semiconductor substrate includes a diffusion layer of a second conductivity type provided on a first main surface side of a drift layer in an IGBT region, a diode region, the wiring region, and the termination region. The diffusion layer includes a base layer in the IGBT region, an anode layer in the diode region, a wiring well layer in the wiring region, and a termination well layer in the termination region. A depth of the base layer is less than depths of a plurality of trench gates, and is equal to or more than depths of the anode layer, the wiring well layer, and the termination well layer.

Abstract: The semiconductor device according to the present application includes: a hole injection region including a hole injection layer and a semiconductor layer of a second conductivity type; a diode region including an anode layer of a second conductivity type and a cathode layer of a first conductivity type; a boundary portion semiconductor layer of a second conductivity type provided between the diode region and the hole injection region and provided on a first main surface side; a carrier injection suppression layer of a first conductivity type provided in a surface layer of the boundary portion semiconductor layer; and a semiconductor layer of a second conductivity type provided to protrude from the hole injection region on a second main surface side.

Abstract: An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

Abstract: A semiconductor device includes: a first control electrode and a second control electrode for switching that are formed in a first main surface and a second main surface, respectively, of a semiconductor substrate; a first control electrode pad electrically connected to the first control electrode; a first through-via penetrating the semiconductor substrate in a thickness direction and including a conductor electrically connecting the first main surface to the second main surface; and a second control electrode pad formed on the first main surface and electrically connected to the second control electrode through the first through-via.

Abstract: The semiconductor substrate has a first principal surface and a second principal surface. The base contact layer is arranged between the base layer and the first principal surface, and forms a part of the first principal surface. The anode contact region is arranged between the anode layer and the first principal surface, forms a part of the first principal surface, and has a second conductivity type impurity concentration peak value higher than that of the anode layer. The anode contact region includes a first anode contact layer having a lower net concentration and a higher first conductivity type impurity concentration than the base contact layer.

Abstract: Provided is a semiconductor device that is easily controlled. The semiconductor device includes a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential, wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.

Abstract: To provide a semiconductor device that includes: a semiconductor substrate provided with a semiconductor portion that is at least one of a gate insulating film, a pn junction, or a drift layer of a terminal region; an insulating film provided on the semiconductor portion; a metal electrode having an opening that overlaps the semiconductor portion in plan view and is provided on a side opposite to the semiconductor portion with respect to the insulating film in cross-sectional view; and a plated electrode provided at at least a portion of an inside of the opening using the metal electrode as a material to be plated.

Abstract: A semiconductor device includes a semiconductor region provided with a semiconductor layer on a main surface side, and a first defect provided in the semiconductor layer and extending from the main surface side in a direction including a component in a thickness direction. The semiconductor region includes at least one of a diode region in which a cathode layer is provided as the semiconductor layer or an IGBT region in which a collector layer is provided as the semiconductor layer.

Abstract: Provided is a semiconductor device in which a first anode layer and a first contact layer are provided on a first main surface side in a diode region, and in which a second anode layer and a second contact layer are provided on the first main surface side in a boundary region. A concentration of impurities of a second conductive type of the second anode layer is lower than a concentration of impurities of the second conductive type of the first anode layer, or an occupied area ratio of the second contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the boundary region is smaller than an occupied area ratio of the first contact layer with respect to the area where the emitter electrode is in contact with the semiconductor substrate in the diode region.

Abstract: Even if there is a change in the shape of a transfer mold power module is required, a change in a position of the electrode of the module is facilitated by separating electrode terminals of a power module from the electrodes and retrofitting the separated electrode terminals to the electrodes with high precision. A semiconductor device includes a mold resin enclosing a semiconductor chip, an electrode electrically connected to the semiconductor chip and exposed in an opening provided in the mold resin, and an electrode terminal having a contact portion that covers the electrode and is in electrical contact with the electrode, a plurality of projections formed to surround the contact portion and provided between a side surface of the opening and the contact portion, a contact end portion having the contact portion and an open end portion which is a different end portion from the contact end portion.

Abstract: A semiconductor device has an alternating region in which insulated gate bipolar transistor (IGBT) regions and diode regions are alternately arranged linearly in a plan view. In the alternating region, a width, in the first direction, of an IGBT region closest to the center of a cell region is equal to or smaller than widths of other IGBT regions in the first direction, and a width, in the first direction, of a diode region closest to a center of the cell region is equal to or smaller than widths of other diode regions in the first direction.

Abstract: A semiconductor device includes: a semiconductor substrate including an upper surface and a lower surface opposing each other and a drift layer of a first conductivity type; a base layer of a second conductivity type; an emitter layer of the first conductivity type and a contact layer of the second conductivity type; an active trench; dummy trenches; a trench gate electrode formed in the active trench; a dummy trench gate electrode formed in each of the dummy trenches; an embedded insulating film formed on the trench gate electrode in the active trench, formed on the dummy trench gate electrode in the dummy trench, and having an upper end lower than the upper surface; and an emitter electrode contacting the emitter layer on the upper surface and an inner wall of the active trench, and contacting the contact layer on the upper surface and an inner wall of the dummy trench.