Patents by Inventor Shinya Sugimori

Shinya Sugimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6967128
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can make a ground/power source potential stable without reducing the number of pins for signals. The semiconductor device includes a plurality of leads, a tab having a size smaller than a size of a semiconductor chip, suspending leads connected to the tab and having suspending lead exposing portions, four bar leads connected to the suspending leads and arranged outside the semiconductor chip, first wires for connecting pads of the semiconductor chip and the leads, second wires for connecting the pads of the semiconductor chip and the bar leads, and a sealing body for sealing the semiconductor chip using resin. On a back surface of the sealing body, a distance between the suspending lead exposing portion and the lead exposing portion is set to a value equal to or more than a distance between the lead exposing portions.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: November 22, 2005
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Shinya Sugimori
  • Publication number: 20040256707
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can make a ground/power source potential stable without reducing the number of pins for signals. The semiconductor device includes a plurality of leads, a tab having a size smaller than a size of a semiconductor chip, suspending leads connected to the tab and having suspending lead exposing portions, four bar leads connected to the suspending leads and arranged outside the semiconductor chip, first wires for connecting pads of the semiconductor chip and the leads, second wires for connecting the pads of the semiconductor chip and the bar leads, and a sealing body for sealing the semiconductor chip using resin. On a back surface of the sealing body, a distance between the suspending lead exposing portion and the lead exposing portion is set to a value equal to or more than a distance between the lead exposing portions.
    Type: Application
    Filed: July 16, 2004
    Publication date: December 23, 2004
    Applicants: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Shinya Sugimori
  • Patent number: 6774464
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can make a ground/power source potential stable without reducing the number of pins for signals. The semiconductor device includes a plurality of leads, a tab having a size smaller than a size of a semiconductor chip, suspending leads connected to the tab and having suspending lead exposing portions, four bar leads connected to the suspending leads and arranged outside the semiconductor chip, first wires for connecting pads of the semiconductor chip and the leads, second wires for connecting the pads of the semiconductor chip and the bar leads, and a sealing body for sealing the semiconductor chip using resin. On a back surface of the sealing body, a distance between the suspending lead exposing portion and the lead exposing portion is set to a value equal to or more than a distance between the lead exposing portions.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: August 10, 2004
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Shinya Sugimori
  • Publication number: 20030227076
    Abstract: The present invention provides a semiconductor device and a manufacturing method thereof which can make a ground/power source potential stable without reducing the number of pins for signals. The semiconductor device includes a plurality of leads, a tab having a size smaller than a size of a semiconductor chip, suspending leads connected to the tab and having suspending lead exposing portions, four bar leads connected to the suspending leads and arranged outside the semiconductor chip, first wires for connecting pads of the semiconductor chip and the leads, second wires for connecting the pads of the semiconductor chip and the bar leads, and a sealing body for sealing the semiconductor chip using resin. On a back surface of the sealing body, a distance between the suspending lead exposing portion and the lead exposing portion is set to a value equal to or more than a distance between the lead exposing portions.
    Type: Application
    Filed: May 20, 2003
    Publication date: December 11, 2003
    Applicants: Hitachi, Ltd., Renesas Northern Japan Semiconductor, Inc.
    Inventor: Shinya Sugimori