Patents by Inventor Shinya Tada

Shinya Tada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10404312
    Abstract: The present disclosure relates to a signal processing apparatus capable of reducing a circuit scale when transmitting and receiving a signal from an antenna. A first n-type MOS transistor amplifies a transmission signal to be transmitted from the antenna. A second n-type MOS transistor supplies a reception signal to be received from the antenna to a reception circuit. The first n-type MOS transistor and the second n-type MOS transistor are connected to the antenna in series. Furthermore, the reception circuit is connected to a contact between the first n-type MOS transistor and the second n-type MOS transistor. The present disclosure is capable of being applied to, for example, a radio transceiver.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 3, 2019
    Assignee: SONY CORPORATION
    Inventors: Naoto Yoshikawa, Shinya Tada
  • Publication number: 20180159581
    Abstract: The present disclosure relates to a signal processing apparatus capable of reducing a circuit scale when transmitting and receiving a signal from an antenna. A first n-type MOS transistor amplifies a transmission signal to be transmitted from the antenna. A second n-type MOS transistor supplies a reception signal to be received from the antenna to a reception circuit. The first n-type MOS transistor and the second n-type MOS transistor are connected to the antenna in series. Furthermore, the reception circuit is connected to a contact between the first n-type MOS transistor and the second n-type MOS transistor. The present disclosure is capable of being applied to, for example, a radio transceiver.
    Type: Application
    Filed: May 20, 2016
    Publication date: June 7, 2018
    Inventors: NAOTO YOSHIKAWA, SHINYA TADA
  • Patent number: 6963139
    Abstract: A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the ?-crystal structure.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: November 8, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takenobu Kishida, Shinya Tada, Atsushi Ikeda, Takeshi Harada, Kohei Sugihara
  • Publication number: 20050035454
    Abstract: A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the ?-crystal structure.
    Type: Application
    Filed: July 2, 2004
    Publication date: February 17, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takenobu Kishida, Shinya Tada, Atsushi Ikeda, Takeshi Harada, Kohei Sugihara
  • Patent number: 6770977
    Abstract: A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the &bgr;-crystal structure.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: August 3, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takenobu Kishida, Shinya Tada, Atsushi Ikeda, Takeshi Harada, Kohei Sugihara
  • Publication number: 20020190352
    Abstract: A barrier layer is formed on an insulating or conducting film provided on a semiconductor substrate, and an electrode or an interconnect made from a conducting film is formed on the barrier layer. The barrier layer includes a tantalum film having the &bgr;-crystal structure.
    Type: Application
    Filed: January 7, 2002
    Publication date: December 19, 2002
    Inventors: Takenobu Kishida, Shinya Tada, Atsushi Ikeda, Takeshi Harada, Kohei Sugihara
  • Publication number: 20010054558
    Abstract: A producing method of the present invention includes (i) forming a wiring line above a semiconductor substrate, (ii) forming an insulating layer above the semiconductor substrate and the wiring line, (iii) forming an opening penetrating the insulating layer in the insulating layer with respect to a portion above the wiring line, (iv) forming a barrier layer whose surface is formed of a material A, so as to cover a surface of the insulating layer and an inner surface of the opening, (v) forming a metal layer made of a first metal on the barrier layer, and (vi) depositing a second metal inside the opening by a plating, thus forming a via plug containing the second metal. A rest potential PA of the material A with respect to the second metal is larger than a rest potential PM of the first metal with respect to the second metal.
    Type: Application
    Filed: March 2, 2001
    Publication date: December 27, 2001
    Inventors: Shinya Tada, Shuji Hirao, Mitsuru Sekiguchi