Patents by Inventor Shinya TAKAMAEDA

Shinya TAKAMAEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966716
    Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 23, 2024
    Assignees: HITACHI, LTD, NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Normann Mertig, Takashi Takemoto, Shinya Takamaeda, Kasho Yamamoto, Masato Motomura, Akira Sakai, Hiroshi Teramoto
  • Publication number: 20210232899
    Abstract: The neural electronic circuit includes: a storage unit (MC) that stores a logarithmic weighting coefficient, in which a value obtained by logarithmizing a weighting coefficient corresponding to input data that is input is expressed in multiple bits, and outputs the logarithmic weighting coefficient bit by bit; a first electronic circuit unit (Pe) that outputs a multiplication result of the input data and the weighting coefficient; and a second electronic circuit unit (Act) that realizes addition and application functions for adding up the multiplication results, applying an activation function to the addition result, and outputting output data. Logarithmic input data expressed in multiple bits is received bit by bit, a logarithmic addition is calculated by adding up the logarithmic input data and the logarithmic weighting coefficient output from the storage unit, the multiplication result is calculated by linearizing the logarithmic addition result, and the output data that is logarithmized is output.
    Type: Application
    Filed: January 25, 2019
    Publication date: July 29, 2021
    Inventors: Shinya Takamaeda, Kodai Ueyoshi, Masato Motomura
  • Publication number: 20210072959
    Abstract: An information processing apparatus includes an annealing control unit, a spin interaction memory, a random number generation unit, and a spin state update unit and obtains a solution by using an Ising model. The annealing control unit controls an annealing step and a parameter of a temperature and a parameter of a self-action. The spin interaction memory stores the interaction coefficient of a spin. The random number generation unit generates a predetermined random number. The spin state update unit includes a spin buffer that stores values of a plurality of spins, an instantaneous magnetic field calculation unit that calculates instantaneous magnetic fields of the plurality of spins, a probability calculation unit that calculates update probabilities of the plurality of spins, and a spin state determination unit that updates the values of the spins based on the update probabilities and a random number.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 11, 2021
    Inventors: Normann MERTIG, Takashi TAKEMOTO, Shinya TAKAMAEDA, Kasho YAMAMOTO, Masato MOTOMURA, Akira SAKAI, Hiroshi TERAMOTO
  • Patent number: 10275392
    Abstract: A data processing device includes a two-dimensional structure including a plurality of stages in a vertical direction, the stages each including basic units in a horizontal direction such that the number of the basic units is equal to the number of ways. The basic units each includes a memory block having a plurality of ports, an address generator for the ports of the memory block, and a calculation unit.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 30, 2019
    Assignee: NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yasuhiko Nakashima, Shinya Takamaeda
  • Publication number: 20180089141
    Abstract: A data processing device includes a two-dimensional structure including a plurality of stages in a vertical direction, the stages each including basic units in a horizontal direction such that the number of the basic units is equal to the number of ways. The basic units each includes a memory block having a plurality of ports, an address generator for the ports of the memory block, and a calculation unit.
    Type: Application
    Filed: April 6, 2016
    Publication date: March 29, 2018
    Applicant: National University Corporation Nara Institute of Science and Technology
    Inventors: Yasuhiko NAKASHIMA, Shinya TAKAMAEDA