Abstract: A multilayer porous membrane with two exterior layers and at least one interior layer. The average pore size of the interior layer is greater than that of either of the two exterior layers. The multilayer porous membrane may be used, for example, as or as part of a battery separator. Compared to prior multilayer porous membranes for battery separators, the multilayer porous membrane herein may exhibit at least one of improved thermal properties, improved anti-metal contamination properties, improved ease of manufacture, and combinations thereof.

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

Abstract: A memory system of an embodiment includes a non-volatile memory and a controller configured to control the accessing of the non-volatile memory according to commands from a host device. The controller is configured to set a mode transition time to a value according to a first command received from the host. The controller transitions from a first operating mode to a second operating mode, in which power supply is suspended to a predetermined circuit, when the time since the last command was received from the host device reaches the mode transition time. The controller maintains the second operating mode until another command is received from the host device.

Abstract: According to one or more embodiments, a memory system includes a signal terminal, a power line, a resistance element, a nonvolatile semiconductor memory, and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The controller is configured to determine whether to connect the signal terminal to the power line via the resistance element.

Abstract: A switch is provided. The switch is connected to a control apparatus for controlling Lawful Interception, and relays packets transmitted and received between a user apparatus and an IMS apparatus in the home network of the user apparatus. The switch includes a determination unit configured to determine whether the user apparatus is a Lawful Interception target or whether the user apparatus is a roaming user; and a transmission unit configured to, in the case where the user apparatus is a Lawful Interception target or in the case where the user apparatus is a roaming user, transmit to a mobile management switch information indicating to the user apparatus that the user apparatus should transmit and receive the packets to and from the IMS apparatus without encryption.

Abstract: A network node is a first network node in a VPLMN (Visited Public land mobile network), the network node including a receiving unit configured to receive information relating to network selection, from a second network node in an HPLMN (Home Public land mobile network); a transmitting unit configured to transmit the information relating to network selection, to a user equipment; and a control unit configured to transmit, to the second network node, a response indicating that the user equipment was unable to receive the information relating to network selection, when a response, with respect to the information relating to network selection transmitted to the user equipment, is not received from the user equipment.

Abstract: A user equipment includes a receiving unit configured to receive, from a network node in a VPLMN (Visited Public land mobile network), information indicating a PLMN to be prioritized and information indicating a trigger of PLMN selection; and a control unit configured to execute the PLMN selection, based on the information indicating the PLMN to be prioritized and the information indicating the trigger of the PLMN selection.

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

Abstract: A disclosed user device includes a receiver configured to receive emergency information from a network; and a control unit configured to change a process of detecting whether first emergency information is duplicated with second emergency information upon receiving, by the receiver, the second emergency information after the first emergency information, based on the first emergency information.

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.

Abstract: A memory system of an embodiment includes a non-volatile memory and a controller configured to control the accessing of the non-volatile memory according to commands from a host device. The controller is configured to set a mode transition time to a value according to a first command received from the host. The controller transitions from a first operating mode to a second operating mode, in which power supply is suspended to a predetermined circuit, when the time since the last command was received from the host device reaches the mode transition time. The controller maintains the second operating mode until another command is received from the host device.

Abstract: According to one or more embodiments, a memory system includes a signal terminal, a power line, a resistance element, a nonvolatile semiconductor memory, and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The controller is configured to determine whether to connect the signal terminal to the power line via the resistance element.

Abstract: A network node for connecting to a plurality of base station devices, the plurality of base station devices each being connected to one or a plurality of core networks belonging to different systems, the network node including a controller that controls delivery of emergency information identical to delivery of emergency information activated by a first core network of the plurality of core networks so that the delivery of the emergency information identical to the delivery of the emergency information activated by the first core network of the plurality of core networks is prevented from being activated by a core network other than the first core network; and a transmitter that transmits a message for a base station device to deliver emergency information.

Abstract: A UE 200 operates as any one of a plurality of categories according to capability. The UE 200 includes: an attach processing unit 220 that performs attaching to a core network; an operation control unit 230 that causes the UE 200 to operate as a restricted category whose capability is restricted as compared to a normal category; and a category notification unit 240 that notifies the core network of a category in which the UE 200 is operating at the time of the attaching or after the attaching.

Abstract: A user apparatus according to an embodiment is provided. The user apparatus communicates with a base station, and includes a determination unit configured to, in the case of making a VoLTE call, determine whether a predetermined indicator is included in broadcast information received from the base station; and a transmission unit configured to transmit to the base station an RRC connection request message in which information is included indicating a request for an RRC connection to be established for making a VoLTE call.

Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.

Abstract: In 5G cell (230) of 5G system (200), upon detecting that access to the 5G system (200) is barred, the 5G system (200) is congested, 5G core network (220) of the 5G system (200) does not support IMS-type communication service, or fallback to 4G system (300) is instructed, UE (100) selects 4G cell (330) of the 4G system (300) as a target cell for connection. The UE (100) transmits a connection request signal for the IMS-type communication service to the target cell for connection.

Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.

Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.