Patents by Inventor Shinya Takeda

Shinya Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10927209
    Abstract: An object of the present invention is to provide an aqueous dispersion for use in a cosmetic, which has both the flexibility and hair styling properties (hair set retention properties), and which allows for easily re-styling hair when the hair style once set has been disturbed; and a cosmetic including the same. In the above mentioned aqueous dispersion and the cosmetic, a polyurethane is used, which is obtainable from a polyol component including at least one type of a polyether polyol and a polyester polyol, and a polyvalent isocyanate component, wherein the polyol component includes: a polyether polyol containing as a major component a structural unit derived from a polyalkylene glycol having from 2 to 4 carbon atoms, and having a number average molecular weight of 400 or more and 4,000 or less; or a polyester polyol containing a structural unit derived from at least one type of dicarboxylic acid selected from the group consisting of phthalic acid, isophthalic acid and terephthalic acid.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 23, 2021
    Assignee: JAPAN COATING RESIN CORPORATION
    Inventors: Shinya Miyata, Eri Hatakeyama, Ryosuke Kawasaki, Aiko Takeda
  • Publication number: 20210043378
    Abstract: A conductive resin layer includes a first region positioned on the end surface, a second region positioned on the side surface, and a third region positioned on a ridge portion between the end surface and the side surface. In a case where a maximum thickness of the first region is T (?m) and a maximum thickness of the second region is T2 (?m), the maximum thickness T1 and the maximum thickness T2 satisfy a relation of T2/T1>0.11. In a cross-section along a thickness direction of the third region, a total area of the voids in the third region is in a range of 3.0 to 11.0% of an area of the third region.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 11, 2021
    Applicant: TDK CORPORATION
    Inventors: Yuichi NAGAI, Takehisa TAMURA, Shinya ONODERA, Ken MORITA, Atsushi TAKEDA
  • Publication number: 20210043385
    Abstract: A conductive resin layer includes a first region positioned on the end surface, a second region positioned on the side surface, and a third region positioned on a ridge portion between the end surface and the side surface. In a case where a maximum thickness of the first region is T1 (?m) and a maximum thickness of the second region is T2 (?m), the maximum thickness T1 and the maximum thickness T2 satisfy a relation of T2/T1?0.11. In a cross-section along a thickness direction of the first region, a total area of voids in the first region is in a range of 5.0 to 36.0% of an area of the first region. In a cross-section along a thickness direction of the second region, a total area of voids in the second region is in the range of 5.0 to 36.0% of an area of the second region.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 11, 2021
    Applicant: TDK CORPORATION
    Inventors: Yuichi NAGAI, Takehisa TAMURA, Shinya ONODERA, Ken MORITA, Atsushi TAKEDA
  • Patent number: 10897783
    Abstract: A user apparatus according to an embodiment is provided. The user apparatus communicates with a base station, and includes a determination unit configured to, in the case of making a VoLTE call, determine whether a predetermined indicator is included in broadcast information received from the base station; and a transmission unit configured to transmit to the base station an RRC connection request message in which information is included indicating a request for an RRC connection to be established for making a VoLTE call.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 19, 2021
    Assignee: NTT DOCOMO, INC.
    Inventors: Yasuharu Konishi, Wuri Andarmawanti Hapsari, Shinya Takeda
  • Patent number: 10884668
    Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroya Shirakura, Kyoko Shoji, Shinya Takeda
  • Publication number: 20200393380
    Abstract: The present invention provides a method for determining a sensitivity to ultraviolet light non-invasively and immediately. A method for determining a UV sensitivity is provided involving: a step of irradiating the skin of a test subject with ultraviolet light to determine the UV sensitivity using the amount of biophotons to be detected within a specific period after the irradiation, wherein 50% or more of the specific period overlaps a period from 1 to 3 minutes after the irradiation.
    Type: Application
    Filed: December 28, 2018
    Publication date: December 17, 2020
    Applicant: KAO CORPORATION
    Inventors: Yu GABE, Shinya KASAMATSU, Osamu OSANAI, Katsuya TAKEDA, Yoko NAKAJIMA
  • Patent number: 10818431
    Abstract: An element body of a rectangular parallelepiped shape includes a first principle surface arranged to constitute a mounting surface, a second principle surface opposing the first principle surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction. An external electrode is disposed at an end portion of the element body in the third direction. The external electrode includes a conductive resin layer formed on the end surface. A thickness of the conductive resin layer gradually increases from the second principle surface toward the first principle surface in the first direction. The conductive resin layer includes a thickest portion at a position near the first principle surface in the first direction.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: October 27, 2020
    Assignee: TDK CORPORATION
    Inventors: Shinya Onodera, Takehisa Tamura, Atsushi Takeda, Ken Morita
  • Publication number: 20200336979
    Abstract: In 5G cell (230) of 5G system (200), upon detecting that access to the 5G system (200) is barred, the 5G system (200) is congested, 5G core network (220) of the 5G system (200) does not support IMS-type communication service, or fallback to 4G system (300) is instructed, UE (100) selects 4G cell (330) of the 4G system (300) as a target cell for connection. The UE (100) transmits a connection request signal for the IMS-type communication service to the target cell for connection.
    Type: Application
    Filed: September 12, 2018
    Publication date: October 22, 2020
    Applicant: NTT DOCOMO, INC.
    Inventors: Kenichiro Aoyagi, Hiroshi Ishikawa, Atsushi Minokuchi, Shinya Takeda
  • Publication number: 20200312551
    Abstract: An electronic component includes an element body and an external electrode disposed on the element body. The element body includes a principal surface arranged to constitute a mounting surface and an end surface adjacent to the principal surface. The external electrode includes a conductive resin layer disposed to continuously cover a part of the principal surface and a part of the end surface, and a plating layer covering the conductive resin layer. The conductive resin layer includes a first region positioned on the end surface and a second region positioned on the principal surface. A maximum thickness of the second region is larger than a maximum thickness of the first region.
    Type: Application
    Filed: March 16, 2020
    Publication date: October 1, 2020
    Applicant: TDK CORPORATION
    Inventors: Yuichi NAGAI, Atsushi TAKEDA, Takehisa TAMURA, Shinya ONODERA
  • Publication number: 20200312550
    Abstract: An electronic component includes an element body and an external electrode. The element body includes a principal surface arranged to constitute a mounting surface and an end surface adjacent to the principal surface. The external electrode includes a conductive resin layer disposed to continuously cover a part of the principal surface and a part of the end surface, and a plating layer covering the conductive resin layer. The conductive resin layer includes a first region positioned on the end surface, a second region positioned on a ridge portion between the end surface and the principal surface, and a third region positioned on the principal surface. In a case where a maximum thickness of the first region is T1 (?m) and a minimum thickness of the second region is T2 (?m), the maximum thickness T1 and the minimum thickness T2 satisfy a relation of T2/T1?0.26.
    Type: Application
    Filed: March 16, 2020
    Publication date: October 1, 2020
    Applicant: TDK CORPORATION
    Inventors: Yuichi NAGAI, Atsushi TAKEDA, Takehisa TAMURA, Shinya ONODERA
  • Publication number: 20200312563
    Abstract: An electronic component includes an element body and an external electrode. The element body includes a side surface and an end surface. The external electrode includes a conductive resin layer disposed over the side surface and the end surface. The conductive resin layer includes a first region positioned on the end surface, a second region positioned on the side surface, and a third region positioned on a ridge portion between the end surface and the side surface. In a case where a maximum thickness of the first region is T1 (?m), a maximum thickness of the second region is T2 (?m), and a minimum thickness of the third region is T3 (?m), the maximum thickness T1 and the maximum thickness T2 satisfy a relation of T2/T1?0.11, and the maximum thickness T1 and the minimum thickness T3 satisfy a relation of T3/T1?0.11.
    Type: Application
    Filed: March 16, 2020
    Publication date: October 1, 2020
    Applicant: TDK CORPORATION
    Inventors: Yuichi NAGAI, Atsushi TAKEDA, Takehisa TAMURA, Shinya ONODERA
  • Publication number: 20200301610
    Abstract: A memory system includes a controller and a non-volatile memory device. The controller is connectable to a host device by a bus conforming to a serial peripheral interface (SPI) standard, and configured to recognize a command signal that is received over the bus immediately after a chip select signal is received over the bus. The non-volatile memory device stores first information indicating a data size, second information indicating a manufacturer ID, third information indicating a device ID, and fourth information. The controller, upon recognizing that the command signal is an identification (ID) read command, outputs to the host device, response information that has the data size indicated by the first information and includes any one of: (i) the second information and the third information, and (ii) the second information, the third information, and the fourth information.
    Type: Application
    Filed: August 29, 2019
    Publication date: September 24, 2020
    Inventors: Hiroya SHIRAKURA, Kyoko SHOJI, Shinya TAKEDA
  • Publication number: 20200294554
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 17, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takayuki KAKEGAWA, Shinya NAITO, Masaki KONDO, Takashi KURUSU, Hiroshi TAKEDA, Nayuta KARIYA
  • Patent number: 10769011
    Abstract: A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunsuke Kodera, Toshihiko Kitazume, Kenichirou Kada, Nobuhiro Tsuji, Shinya Takeda, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
  • Patent number: 10760524
    Abstract: An internal combustion engine includes an engine main body defining a cylinder bore, a piston received in the cylinder bore, and a crankshaft rotatably supported by the engine main body and connected with the piston via a connecting rod, the piston including a skirt. The cylinder bore includes a first region defined as a range along the cylinder axial line on a side of a top dead center from a first piston position, and a second region defined as a range along the cylinder axial line on a side of the bottom dead center from a second piston position closer to the bottom dead center than the first piston position, and a connection region positioned between the first and second regions. A diameter of the cylinder bore is smaller in the first region than in the second region, and the connection region connects the first and second regions smoothly.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: September 1, 2020
    Assignee: Honda Motor Co., Ltd.
    Inventors: Naoaki Takeda, Naokazu Kawase, Yoshihiro Okada, Shinya Abe, Hidehumi Kuramitsu
  • Patent number: 10763042
    Abstract: An element body of a rectangular parallelepiped shape includes a first principal surface arranged to constitute a mounting surface, a second principal surface opposing the first principal surface in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction. An external electrode is disposed at an end portion of the element body in the third direction. A first length of the element body in the first direction is different from a second length of the element body in the second direction. The external electrode includes a conductive resin layer. The conductive resin layer continuously covers one part of the first principal surface, one part of the end surface, and one part of each of the pair of side surfaces.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK CORPORATION
    Inventors: Shinya Onodera, Takehisa Tamura, Atsushi Takeda, Ken Morita
  • Patent number: 10755859
    Abstract: An element body of a rectangular parallelepiped shape includes a pair of principal surfaces opposing each other in a first direction, a pair of side surfaces opposing each other in a second direction, and a pair of end surfaces opposing each other in a third direction. An external electrode disposed on an end portion of the element body in the third direction. When viewed from the third direction, a width of the element body in the second direction is the largest at a central position in the first direction, and gradually decreases from the central portion in the first direction. When viewed from the third direction, a position in which a length from one end to another end of the conductive resin layer in the second direction is the largest is located closer to the one principal surface than the central position.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 25, 2020
    Assignee: TDK CORPORATION
    Inventors: Shinya Onodera, Takehisa Tamura, Ken Morita, Atsushi Takeda
  • Patent number: 10732863
    Abstract: A memory system includes a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device, and a memory that includes a plurality of blocks. When the command is a first command, the controller outputs to the host device, information indicating whether at least one of a write operation and an erase operation with respect to at least one particular block is prohibited.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shunsuke Kodera, Kenichirou Kada, Shinya Takeda, Kiyotaka Hayashi, Yoshio Furuyama, Tetsuya Iwata, Wangying Lin
  • Publication number: 20200211774
    Abstract: An electronic component includes an element body and an external electrode disposed on the element body. The external electrode includes a sintered metal layer, a conductive resin layer disposed on the sintered metal layer, and a solder plating layer arranged to constitute an outermost layer of the external electrode. A space exists in the conductive resin layer or between the conductive resin layer and the sintered metal layer. A first maximum length of the space in a thickness direction of the conductive resin layer is shorter than a second maximum length of the space in a direction orthogonal to the thickness direction of the conductive resin layer.
    Type: Application
    Filed: December 23, 2019
    Publication date: July 2, 2020
    Applicant: TDK CORPORATION
    Inventors: Shinya ONODERA, Takehisa TAMURA, Atsushi TAKEDA, Yuichi NAGAI
  • Publication number: 20200211775
    Abstract: An electronic component includes an element body and an external electrode disposed on the element body. The external electrode includes a conductive resin layer, a solder plating layer arranged to constitute an outermost layer of the external electrode, and an intermediate plating layer disposed between the conductive resin layer and the solder plating layer. The intermediate plating layer has better solder leach resistance than metal contained in the conductive resin layer. An opening is formed in the intermediate plating layer. The solder plating layer is formed on the conductive resin layer through the opening.
    Type: Application
    Filed: December 23, 2019
    Publication date: July 2, 2020
    Applicant: TDK CORPORATION
    Inventors: Shinya ONODERA, Takehisa TAMURA, Atsushi TAKEDA, Yuichi NAGAI