Patents by Inventor Shinya Takyu

Shinya Takyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9893116
    Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Takyu, Hideo Numata, Hiroyuki Okura
  • Publication number: 20160079303
    Abstract: A manufacturing method of an electronic device processes a surface of a first wafer, bonds a surface of a second wafer to the processed surface of the first wafer, thins the first wafer by polishing a back surface of the first wafer, the back surface being located on an opposite side of the processed surface, forms a groove along a periphery of the back surface of the thinned first wafer by using a dicing blade, attaches a protective layer to the back surface of the first wafer having the groove, via a bonding layer, and polishes a back surface of the second wafer, the back surface being located on an opposite side of the surface attached to the protective layer.
    Type: Application
    Filed: March 13, 2015
    Publication date: March 17, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shinya Takyu, Hideo Numata, Hiroyuki Okura
  • Patent number: 8956917
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Shinya Takyu, Akira Tomono
  • Patent number: 8790995
    Abstract: According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Noriko Shimizu, Tsutomu Fujita
  • Patent number: 8771456
    Abstract: According to one embodiment, there is disclosed a method of manufacturing a semiconductor device forming a release layer on a region excluding a peripheral edge portion of a surface of a first substrate, bonding a second substrate to at least a region including the release layer of the surface of the first substrate via an adhesive layer, removing physically a peripheral edge portion of the second substrate in a manner that at least a surface of the adhesive layer right under the peripheral edge portion of the second substrate is exposed, the adhesive layer is caused to remain between the peripheral edge portion of the first substrate and the second substrate, and adhesion between the first and second substrates is maintained, and then dissolving the adhesive layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noriko Shimizu, Shinya Takyu
  • Publication number: 20130248099
    Abstract: According to one embodiment, there is disclosed a method of manufacturing a semiconductor device forming a release layer on a region excluding a peripheral edge portion of a surface of a first substrate, bonding a second substrate to at least a region including the release layer of the surface of the first substrate via an adhesive layer, removing physically a peripheral edge portion of the second substrate in a manner that at least a surface of the adhesive layer right under the peripheral edge portion of the second substrate is exposed, the adhesive layer is caused to remain between the peripheral edge portion of the first substrate and the second substrate, and adhesion between the first and second substrates is maintained, and then dissolving the adhesive layer.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noriko SHIMIZU, Shinya Takyu
  • Publication number: 20130001766
    Abstract: According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone.
    Type: Application
    Filed: March 16, 2012
    Publication date: January 3, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinya TAKYU, Noriko Shimizu, Tsutomu Fujita
  • Publication number: 20120329369
    Abstract: According to one embodiment, a substrate processing method will be disclosed. The method includes attaching a substrate to be processed onto a supporting substrate via an adhesive layer, removing an outer peripheral edge portion of the substrate to be processed together with the adhesive sticking to the outer peripheral edge portion, and grinding a surface of a side opposite to the supporting substrate of the substrate to be processed whose outer peripheral edge portion is removed.
    Type: Application
    Filed: March 15, 2012
    Publication date: December 27, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noriko SHIMIZU, Shinya TAKYU
  • Patent number: 8294282
    Abstract: The present invention provides a semiconductor device which comprises a substrate, a first semiconductor chip on a substrate, a second semiconductor chip on the first semiconductor chip, and an adhesive sheet between the first and second semiconductor chips. The second semiconductor chip has a mirrored back surface, and the adhesive sheet contains a metal impurity ion trapping agent.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidekazu Hayashi, Hiroshi Tomita, Junya Sagara, Shinya Takyu, Norihiro Togasaki, Tetsuya Kurosawa, Yukiko Kitajima
  • Publication number: 20120235282
    Abstract: According to one embodiment, a semiconductor device manufacturing method is disclosed. The method comprises (a) forming cut grooves in a front surface of a semiconductor wafer on which semiconductor elements are formed to partition the front surface into a plurality of regions, (b) disposing partly a resin in the cut grooves, (c) adhering a protection tape on the front surface of the semiconductor wafer, (d) thinning the semiconductor wafer by grinding a rear surface of the semiconductor wafer to reach the cut grooves, (e) forming an adhesive agent layer on the rear surface of the semiconductor wafer, and (f) dividing the semiconductor wafer into a plurality of semiconductor chips by cutting the adhesive agent layer together with the disposed resin along the cut grooves.
    Type: Application
    Filed: February 14, 2012
    Publication date: September 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira TOMONO, Tetsuya KUROSAWA, Tsutomu FUJITA, Mika KIRITANI, Shinya TAKYU
  • Publication number: 20120187542
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The method includes: (a) forming cutting grooves in an element formation surface of a semiconductor wafer on which semiconductor elements are formed; (b) applying a protection tape on the element formation surface of the semiconductor wafer; (c) grinding a rear surface of the semiconductor wafer to thin the semiconductor wafer and to divide the semiconductor wafer into a plurality of semiconductor chips on which the semiconductor elements are formed; (d) forming an adhesive layer on the rear surface of the semiconductor wafer; (e) separating and cutting the adhesive layer for each of the semiconductor chips; and (f) removing the protection tape. The (e) is performed by spraying a high-pressure air to the adhesive layer formed on the rear surface of the semiconductor wafer while melting or softening the adhesive layer by heating.
    Type: Application
    Filed: January 19, 2012
    Publication date: July 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya KUROSAWA, Shinya Takyu, Akira Tomono
  • Publication number: 20110163459
    Abstract: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
    Type: Application
    Filed: March 18, 2011
    Publication date: July 7, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junya Sagara, Shinya Takyu, Tetsuya Kurosawa
  • Patent number: 7932162
    Abstract: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: April 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Sagara, Shinya Takyu, Tetsuya Kurosawa
  • Publication number: 20110068480
    Abstract: The present invention provides a semiconductor device which comprises a substrate, a first semiconductor chip on a substrate, a second semiconductor chip on the first semiconductor chip, and an adhesive sheet between the first and second semiconductor chips. The second semiconductor chip has a mirrored back surface, and the adhesive sheet contains a metal impurity ion trapping agent.
    Type: Application
    Filed: March 23, 2010
    Publication date: March 24, 2011
    Inventors: Hidekazu Hayashi, Hiroshi Tomita, Junya Sagara, Shinya Takyu, Norihiro Togasaki, Tetsuya Kurosawa, Yukiko Kitajima
  • Publication number: 20100311224
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes forming a plurality of first trenches in a semiconductor substrate, forming an insulating member in the first trenches, removing a part of a portion of the insulating member, forming second trenches in the insulating member, and attaching a protection film. The semiconductor substrate has a first and a second main surface. The insulating member has an upper face located higher than the first main surface. The portion is located higher than the first main surface.
    Type: Application
    Filed: May 18, 2010
    Publication date: December 9, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Kurosawa, Junya Sagara, Shinya Takyu, Norihiro Togasaki
  • Patent number: 7833836
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: November 16, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani
  • Patent number: 7631680
    Abstract: An adhesive tape peeling mechanism has an adhering section and a porous member. The adhering section adheres to a segmented semiconductor wafer bonded to adhesive tape. The porous member is provided on the surface adhering to the semiconductor wafer of the adhering section. The porous member is divided into at least two adhering areas in the direction in which the adhesive tape is peeled. The porous member adheres to the semiconductor wafer by suction and fixes the wafer in place.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: December 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Kurosawa, Shinya Takyu
  • Publication number: 20090111218
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Application
    Filed: December 31, 2008
    Publication date: April 30, 2009
    Inventors: Shinya TAKYU, Kazuhiro Iizuka, Mika Kiritani
  • Publication number: 20090096110
    Abstract: A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Junya SAGARA, Shinya TAKYU, Tetsuya KUROSAWA
  • Patent number: 7482695
    Abstract: A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: January 27, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Takyu, Kazuhiro Iizuka, Mika Kiritani