Patents by Inventor Shinya Terao

Shinya Terao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210160968
    Abstract: A heater includes a base body and a resistance heating element. The base body is configured by an insulating material and includes a top surface on which a wafer is placed. The resistance heating element extends in the base body along the top surface. A top surface of the resistance heating element and the base body are in contact with each other. A vacuum or gas-filled gap is interposed between a side surface of the resistance heating element and the base body.
    Type: Application
    Filed: April 24, 2019
    Publication date: May 27, 2021
    Inventors: Yasunori KAWANABE, Yoshihiro OKAWA, Yuusaku ISHIMINE, Shinya TERAO
  • Patent number: 6469259
    Abstract: A wiring board of the present invention readily controls a power source voltage and unwanted irradiation noises developed across a power source layer and a ground layer over a broad range of frequencies with a simple arrangement. The wiring board has an on-board surface on the surface of a dielectric substrate, on which a semiconductor device or the like is mounted, and a power source layer and a ground layer, which are made of a conductor material principally composed of at least one kind of element selected from Cu, W, and Mo, are provided on the back surface of the dielectric substrate or within the same. The periphery of at least one of low resistance areas of the power source layer and ground layer, respectively is provided with a corresponding high resistance area having a higher sheet resistance than that of the respective low resistance areas.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: October 22, 2002
    Assignee: Kyocera Corporation
    Inventors: Yoshihiro Takeshita, Shinya Terao, Satoru Takenouchi, Masaki Kaji, Ryuji Koga
  • Publication number: 20010050182
    Abstract: A wiring board of the present invention readily controls a power source voltage and unwanted irradiation noises developed across a power source layer and a ground layer over a broad range of frequencies with a simple arrangement. The wiring board has an on-board surface on the surface of a dielectric substrate, on which a semiconductor device or the like is mounted, and a power source layer and a ground layer, which are made of a conductor material principally composed of at least one kind of element selected from Cu, W, and Mo, are provided on the back surface of the dielectric substrate or within the same. The periphery of at least one of low resistance areas of the power source layer and ground layer, respectively is provided with a corresponding high resistance area having a higher sheet resistance than that of the respective low resistance areas.
    Type: Application
    Filed: February 27, 2001
    Publication date: December 13, 2001
    Inventors: Yoshihiro Takeshita, Shinya Terao, Satoru Takenouchi, Masaki Kaji, Ryuji Koga
  • Patent number: 6288347
    Abstract: A wiring board for flip-chip-mounting in which a conductor layer is provided in a portion under the semiconductor element-mounting surface of the ceramic insulating board, the electrically conducting layer being electrically independent from the wiring pattern that is flip-chip-connected. The insulating board is effectively suppressed from deforming such as from warping or undulating. In particular, the semiconductor element-mounting surface exhibits a high degree of flatness. Therefore, the wiring board exhibits a high junction reliability at the flip-chip-connected portions, and is very useful as a semiconductor package or as a hybrid integrated circuit that is used in various electronic devices being mounted on the vehicles.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: September 11, 2001
    Assignees: Kyocera Corporation, Denso Corporation
    Inventors: Shoichi Nakagawa, Takashi Yamasaki, Shinya Terao
  • Patent number: 6217990
    Abstract: A multilayer circuit board for holding a flip chip thereon includes laminated first to fourth substrates. A first pattern integrated portion having a locally high pattern density is provided on the second substrate. Further, on the fourth substrate which is disposed on an opposite side of the second substrate with respect to a center in a laminated direction of the circuit board, a second pattern integrated portion having a locally high pattern density is disposed to correspond to the first pattern integrated portion. Accordingly, a local warp can be prevented from being produced on the mounting surface of the multilayer circuit board when the circuit board is manufactured by baking.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: April 17, 2001
    Assignees: Denso Corporation, Kyocera Corporation
    Inventors: Yasutomi Asai, Takashi Nagasaka, Shinji Ota, Takashi Yamazaki, Shinya Terao, Syoichi Nakagawa