Patents by Inventor Shinya UMEKI
Shinya UMEKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240405016Abstract: A semiconductor module includes an IGBT device, and a MISFET device that composes a parallel circuit together with the IGBT device. The semiconductor module generates a drain current of the MISFET device in a voltage range less than a built-in voltage of the IGBT device and generates a collector current of the IGBT device and a drain current of the MISFET device in a voltage range equal to or more than the built-in voltage.Type: ApplicationFiled: August 13, 2024Publication date: December 5, 2024Inventor: Shinya UMEKI
-
Publication number: 20240379662Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that includes a second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface.Type: ApplicationFiled: July 19, 2024Publication date: November 14, 2024Applicant: ROHM CO., LTD.Inventor: Shinya UMEKI
-
Patent number: 12074161Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that a includes second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface.Type: GrantFiled: June 22, 2023Date of Patent: August 27, 2024Assignee: ROHM CO., LTD.Inventor: Shinya Umeki
-
Publication number: 20240282846Abstract: Provided is a semiconductor device including a semiconductor layer which has opposing first and second principal surfaces, an IGBT region which is formed in the semiconductor layer, a diode region which is formed in the semiconductor layer and adjacent to the IGBT region, a first impurity region of a first conductivity type which is formed inside the semiconductor layer.Type: ApplicationFiled: May 2, 2024Publication date: August 22, 2024Applicant: ROHM CO., LTD.Inventor: Shinya UMEKI
-
Publication number: 20240234267Abstract: A semiconductor device comprises: a first semiconductor chip including a first obverse surface and a first reverse surface spaced apart from each other in a thickness direction; a second semiconductor chip including a second obverse surface and a second reverse surface spaced apart from each other in the thickness direction, and electrically connected in series to the first semiconductor chip; and a conductive member including a first conductive plate electrically connected to the first semiconductor chip and the second semiconductor chip. At least one of the first semiconductor chip and the second semiconductor chip is an IGBT including a collector electrode, an emitter electrode, and a gate electrode. The first conductive plate is provided between the first semiconductor chip and the second semiconductor chip in the thickness direction.Type: ApplicationFiled: March 20, 2024Publication date: July 11, 2024Applicant: ROHM CO., LTD.Inventors: Shinya UMEKI, Yuta KAWAMOTO, Ryosuke FUKUDA
-
Publication number: 20240178223Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge (L2/SD), the dispersion degree is not less than 2 and not more than 15.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Applicant: ROHM CO., LTD.Inventor: Shinya UMEKI
-
Patent number: 11929365Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge (L2/SD), the dispersion degree is not less than 2 and not more than 15.Type: GrantFiled: October 17, 2019Date of Patent: March 12, 2024Assignee: ROHM CO., LTD.Inventor: Shinya Umeki
-
Publication number: 20230335548Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that includes a second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface.Type: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Applicant: ROHM CO., LTD.Inventor: Shinya UMEKI
-
Patent number: 11728333Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that includes a second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface, a boundary region that includes a second-conductivity-type well region formed in the surface layer portion ofType: GrantFiled: May 29, 2019Date of Patent: August 15, 2023Assignee: ROHM CO., LTD.Inventor: Shinya Umeki
-
Publication number: 20230187498Abstract: A semiconductor device includes a first conductive type semiconductor layer which has a principal surface, a second conductive type well region which demarcates an active region and an outer region on the principal surface and is formed on a surface layer portion of the principal surface and includes a high concentration portion high in impurity concentration on the active region side and includes a low concentration portion lower in impurity concentration than the high concentration portion on the outer region side, and a second conductive type impurity region of the active region which is formed on a surface layer portion of the principal surface.Type: ApplicationFiled: June 4, 2021Publication date: June 15, 2023Applicant: ROHM CO., LTD.Inventor: Shinya UMEKI
-
Publication number: 20220344328Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate that has a first main surface on one side and a second main surface on another side, a second-conductivity-type well region that is formed in a surface layer portion of the first main surface and that demarcates an active region and an outer region in the semiconductor substrate, an IGBT including a second-conductivity-type collector region formed at the active region in a surface layer portion of the second main surface and an FET structure formed at the active region in the first main surface, and a diode that includes a first-conductivity-type cathode region formed only at the outer region in the surface layer portion of the second main surface and that has the well region serving as an anode region.Type: ApplicationFiled: September 15, 2020Publication date: October 27, 2022Inventor: Shinya UMEKI
-
Publication number: 20210384190Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Loge (L2/SD), the dispersion degree is not less than 2 and not more than 15.Type: ApplicationFiled: October 17, 2019Publication date: December 9, 2021Inventor: Shinya UMEKI
-
Publication number: 20210210485Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer that includes a first main surface on one side and a second main surface on the other side, an IGBT region that includes an FET structure and a second-conductivity-type collector region formed in a surface layer portion of the second main surface, the FET structure including a second-conductivity-type body region formed in a surface layer portion of the first main surface, a first-conductivity-type emitter region formed in a surface layer portion of the body region, and a gate electrode that faces both the body region and the emitter region across a gate insulating layer, a diode region that includes a second-conductivity-type first impurity region formed in the surface layer portion of the first main surface and a first-conductivity-type second impurity region formed in the surface layer portion of the second main surface, a boundary region that includes a second-conductivity-type well region formed in the surface layer portion ofType: ApplicationFiled: May 29, 2019Publication date: July 8, 2021Inventor: Shinya UMEKI
-
Patent number: 10069017Abstract: A diode includes an n type semiconductor layer including an n type cathode layer and an n type drift layer that has an impurity concentration lower than the n type cathode layer and that is disposed on the n type cathode layer, a p type anode layer disposed at a surface part of the n type drift layer, a p type hole implantation layer selectively disposed at the n type cathode layer, an anode electrode electrically connected to the p type anode layer, and a cathode electrode electrically connected to the n type cathode layer and to the p type hole implantation layer, and the p type hole implantation layer has a diameter of 20 ?m or more.Type: GrantFiled: March 24, 2017Date of Patent: September 4, 2018Assignee: ROHM CO., LTD.Inventor: Shinya Umeki
-
Publication number: 20170278982Abstract: A diode includes an n type semiconductor layer including an n type cathode layer and an n type drift layer that has an impurity concentration lower than the n type cathode layer and that is disposed on the n type cathode layer, a p type anode layer disposed at a surface part of the n type drift layer, a p type hole implantation layer selectively disposed at the n type cathode layer, an anode electrode electrically connected to the p type anode layer, and a cathode electrode electrically connected to the n type cathode layer and to the p type hole implantation layer, and the p type hole implantation layer has a diameter of 20 ?m or more.Type: ApplicationFiled: March 24, 2017Publication date: September 28, 2017Inventor: Shinya UMEKI