Patents by Inventor Shinya Yasue

Shinya Yasue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4115796
    Abstract: Formation of well-regions of a conductivity type opposite to that of a substrate is achieved in such a manner to determine a first threshold voltage level. Ion implantation is effected on desirably selected gates in the respective channels formed on the substrate and the well-regions. Two channels on the ion implanted substrate and on the well-region in which the ion implantation is not effected, are coupled to form a complementary-MOS transistor pair having a first threshold voltage level. The channels on the substrate in which the ion implantation is not effected and on the ion implanted well-region are coupled to form another complementary-MOS transistor pair having a second threshold voltage level.
    Type: Grant
    Filed: April 5, 1977
    Date of Patent: September 19, 1978
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeo Fujimoto, Yasuo Torimaru, Shin-ichi Ogawa, Shinya Yasue