Patents by Inventor Shiori Idaka

Shiori Idaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9543252
    Abstract: A plurality of semiconductor devices provided on a silicon carbide substrate are provided with electrode layers, respectively. The silicon carbide substrate is cut at a region of an exposed surface of the silicon carbide substrate that separates the electrode layers to individually separate the semiconductor devices. A stress relaxation resin is applied to each individually separated semiconductor device to cover the exposed surface at a peripheral end portion of that surface of the semiconductor device which has the electrode layer thereon. A semiconductor apparatus can thus be obtained that also allows a semiconductor device with a silicon carbide or similar compound semiconductor substrate to adhere to a sealant resin via large adhesive strength and thus allows the sealant resin to be less crackable, less peelable and the like by thermal stress caused in operation.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: January 10, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mamoru Terai, Shiori Idaka, Kei Yamamoto, Yoshiyuki Nakaki
  • Patent number: 9385007
    Abstract: A plurality of semiconductor elements for power control are formed on a semiconductor substrate. A stress relaxation resin layer covering a crossing region where band-shaped dicing areas dividing the semiconductor elements adjacent to each other cross is formed. The crossing region is diced to cut the stress relaxation resin layer to obtain the separate semiconductor elements. Accordingly, even with semiconductor elements produced with a compound semiconductor substrate of SiC or the like, a semiconductor device having high adhesive strength with a sealing resin and being less likely to cause cracking or peeling of the sealing resin due to thermal stress during an operation can be obtained.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: July 5, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mamoru Terai, Shiori Idaka, Yoshiyuki Nakaki, Yoshiyuki Suehiro
  • Patent number: 9299628
    Abstract: A power semiconductor module is provided which is capable of keeping low the degrees of increases in temperatures of wide bandgap semiconductor elements, reducing the degree of increase in chip's total surface area of the wide bandgap semiconductor elements, and being fabricated at low costs, when Si semiconductor elements and the wide bandgap semiconductor elements are placed within one and the same power semiconductor module. The Si semiconductor elements are placed in a central region of the power semiconductor module, and the wide bandgap semiconductor elements are placed on opposite sides relative to the central region or in edge regions surrounding the central region.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayoshi Miki, Yasushi Nakayama, Takeshi Oi, Kazuhiro Tada, Shiori Idaka, Shigeru Hasegawa, Tomohiro Kobayashi, Yukio Nakashima
  • Patent number: 9129885
    Abstract: A power semiconductor module in which temperature rise of switching elements made of a Si semiconductor can be suppressed low and efficiency of cooling the module can be enhanced. To that end, the power semiconductor module includes switching elements made of the Si semiconductor and diodes made of a wide-bandgap semiconductor, the diodes are arranged in the middle region of the power semiconductor module, and the switching elements are arranged in both sides or in the periphery of the middle region of the power semiconductor module.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: September 8, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasushi Nakayama, Takayoshi Miki, Takeshi Oi, Kazuhiro Tada, Shiori Idaka, Shigeru Hasegawa, Takeshi Tanaka
  • Publication number: 20150171026
    Abstract: A plurality of semiconductor devices provided on a silicon carbide substrate are provided with electrode layers, respectively. The silicon carbide substrate is cut at a region of an exposed surface of the silicon carbide substrate that separates the electrode layers to individually separate the semiconductor devices. A stress relaxation resin is applied to each individually separated semiconductor device to cover the exposed surface at a peripheral end portion of that surface of the semiconductor device which has the electrode layer thereon. A semiconductor apparatus can thus be obtained that also allows a semiconductor device with a silicon carbide or similar compound semiconductor substrate to adhere to a sealant resin via large adhesive strength and thus allows the sealant resin to be less crackable, less peelable and the like by thermal stress caused in operation.
    Type: Application
    Filed: July 11, 2012
    Publication date: June 18, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Mamoru Terai, Shiori Idaka, Kei Yamamoto, Yoshiyuki Nakaki
  • Publication number: 20150162219
    Abstract: A plurality of semiconductor elements for power control are formed on a semiconductor substrate. A stress relaxation resin layer covering a crossing region where band-shaped dicing areas dividing the semiconductor elements adjacent to each other cross is formed. The crossing region is diced to cut the stress relaxation resin layer to obtain the separate semiconductor elements. Accordingly, even with semiconductor elements produced with a compound semiconductor substrate of SiC or the like, a semiconductor device having high adhesive strength with a sealing resin and being less likely to cause cracking or peeling of the sealing resin due to thermal stress during an operation can be obtained.
    Type: Application
    Filed: July 11, 2012
    Publication date: June 11, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Mamoru Terai, Shiori Idaka, Yoshiyuki Nakaki, Yoshiyuki Suehiro
  • Publication number: 20140138707
    Abstract: A power semiconductor module is provided which is capable of keeping low the degrees of increases in temperatures of wide bandgap semiconductor elements, reducing the degree of increase in chip's total surface area of the wide bandgap semiconductor elements, and being fabricated at low costs, when Si semiconductor elements and the wide bandgap semiconductor elements are placed within one and the same power semiconductor module. The Si semiconductor elements are placed in a central region of the power semiconductor module, and the wide bandgap semiconductor elements are placed on opposite sides relative to the central region or in edge regions surrounding the central region.
    Type: Application
    Filed: July 5, 2012
    Publication date: May 22, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takayoshi Miki, Yasushi Nakayama, Takeshi Oi, Kazuhiro Tada, Shiori Idaka, Shigeru Hasegawa, Tomohiro Kobayashi, Yukio Nakashima
  • Patent number: 8575745
    Abstract: A power semiconductor device includes a conductive insertion member as an external terminal projecting from a surface of the power semiconductor device facing a printed wiring board. The printed wiring board includes a conductive fitting member mounted on a pad part of the printed wiring board. The fitting member receives the insertion member therein when the power semiconductor device is connected to the printed wiring board. The insertion member has a recessed portion formed on a side surface of the insertion member. The fitting member has a projecting portion with elasticity formed on an inner side surface of the fitting member. The elasticity causes the projecting portion of the fitting member to contact the recessed portion of the insertion member under pressure when the insertion member is inserted into the fitting member.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: November 5, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiji Oka, Shiori Idaka, Hiroshi Yoshida
  • Publication number: 20120286292
    Abstract: A power semiconductor module in which temperature rise of switching elements made of a Si semiconductor can be suppressed low and efficiency of cooling the module can be enhanced. To that end, the power semiconductor module includes switching elements made of the Si semiconductor and diodes made of a wide-bandgap semiconductor, the diodes are arranged in the middle region of the power semiconductor module, and the switching elements are arranged in both sides or in the periphery of the middle region of the power semiconductor module.
    Type: Application
    Filed: January 12, 2011
    Publication date: November 15, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasushi Nakayama, Takayoshi Miki, Takeshi Oi, Kazuhiro Tada, Shiori Idaka, Shigeru Hasegawa, Takeshi Tanaka
  • Publication number: 20120187554
    Abstract: A power semiconductor device includes a conductive insertion member as an external terminal projecting from a surface of the power semiconductor device facing a printed wiring board. The printed wiring board includes a conductive fitting member mounted on a pad part of the printed wiring board. The fitting member receives the insertion member therein when the power semiconductor device is connected to the printed wiring board. The insertion member has a recessed portion formed on a side surface of the insertion member. The fitting member has a projecting portion with elasticity formed on an inner side surface of the fitting member. The elasticity causes the projecting portion of the fitting member to contact the recessed portion of the insertion member under pressure when the insertion member is inserted into the fitting member.
    Type: Application
    Filed: September 1, 2011
    Publication date: July 26, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Seiji OKA, Shiori Idaka, Hiroshi Yoshida
  • Patent number: 7951699
    Abstract: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the solder paste is ref lowed, a third step of bonding the metal posts of the mother chip and metal posts of a daughter chip to each other in a thermocompression bonding manner by means of the solder film after the second step, and a fourth step of flip-chip-connecting the mother chip on a circuit substrate by using the solder balls. In the second step, the mother chip is heated in a nitrogen atmosphere in which the oxygen concentration is 500 ppm or less.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 31, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iwasaki, Shiori Idaka, Yasumichi Hatanaka
  • Publication number: 20070141750
    Abstract: A method of manufacturing a semiconductor device includes a first step of forming solder film on metal posts of a mother chip, a second step of forming solder balls after the first step by printing a solder paste on the mother chip and heating the mother chip so that the solder paste is ref lowed, a third step of bonding the metal posts of the mother chip and metal posts of a daughter chip to each other in a thermocompression bonding manner by means of the solder film after the second step, and a fourth step of flip-chip-connecting the mother chip on a circuit substrate by using the solder balls. In the second step, the mother chip is heated in a nitrogen atmosphere in which the oxygen concentration is 500 ppm or less.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 21, 2007
    Inventors: Toshihiro Iwasaki, Shiori Idaka, Yasumichi Hatanaka