Abstract: The present invention relates to a method for forming a static random access memory (SRAM) cell. In order to avoid constantly reducing operating voltage of the SRAM cell affecting the unit stability and noise jamming of the SRAM cell during read/write processes, the invention employs different thicknesses of gate oxide layers of an access transistor and a pull down transistor. Thereby, not only the &bgr; ratio is increased, but also the unit area is decreased.

Abstract: The invention is a mask pattern comprising a first region that is strip-shaped and has two long sides and two short sides, and two second regions that are strip-shaped with each region having two long sides and two short sides, in which the short sides of the second regions are shorter than the sides of the first region, and the second regions extend in a lengthwise direction from the two short sides of the first region, respectively, with the short sides of the second regions adjacent to the short sides of the first region. The mask pattern is used to define a floating gate region in a flash memory.

Abstract: A method for fabricating poly-spacers used in a semiconductor substrate, comprising: forming an undoped first polysilicon layer on the semiconductor substrate; performing a first ion implantation with a first angle to implant impurities into the first polysilicon layer; performing a second ion implantation with a second angle to implant the impurities into the first polysilicon layer; forming a second polysilicon layer on the first polysilicon layer; and etching the first polysilicon layer and the second polysilicon layer to form spacers.

Abstract: A method of fabricating a flash memory is disclosed: firstly, a P-type silicon substrate is divided into a PMOS area, an NMOS area, and a flash memory area. The first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed. The first photo resist is then formed to define the gate pattern of the flash cell array, and then a process of N+ ion implantation is performed to form the source and drain of the flash cell array. After stripping the first photo resist, the second photo resist is formed to define the gate pattern at the NMOS area, and a process of N+ ion implantation is performed to form the NLDD structure. After stripping the second photo resist, the first sidewall is formed, and then a process of N− ion implantation is performed to form the NMOS source/drain. The third photo resist is then formed to define the gate pattern at the PMOS area.

Abstract: A gate oxide and a first conducting layer are formed on a substrate, and then the first conducting layer is patterned and a gate in a NMOS region is formed. A LDD, a sidewall spacer, and a drain/source in the NMOS region are then formed in series. A layer of hard mask is formed. The layer of hard mask and the first conducting layer are patterned and a gate in a PMOS region is formed. A LDD, a sidewall spacer, and a drain/source in the NMOS region are then formed in series.