Abstract: A memory apparatus includes a main memory, a redundant memory, and a substitution control unit. The main memory is configured to receive a read address and output a main data word comprising a plurality of main data sub-words where the read address includes a first portion and a second portion. The redundant memory is configured to receive the read address first portion and output a redundant data sub-word. The substitution control unit includes a substitution control word memory configured to store a plurality of substitution control words and configured to receive the read address first portion and assert a substitution control word including a substitution address second portion. The read address first portion and substitution address second portion form a substitution address. The substitution control unit asserts a substitution control signal when there is a match between the read address and the substitution address.

Abstract: A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

Abstract: A method for fabricating a capacitor electrode on a semiconductor substrate includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through an interfering exposure step; and pattering the conducting layer using the patterned photoresist layer as a mask, thereby forming a capacitor electrode.

Abstract: An input buffer capable of high voltage operation includes a transmission gate connected to a boosting voltage source. The input buffer can be used to maintain the processing speed and noise margin of a digital circuit even through the input voltage thereof is excessively high. Moreover, the input buffer can be used in an address latch or inverter-type circuit.

Abstract: A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

Abstract: A method for fabricating a capacitor electrode on a semiconductor substrate includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through an interfering exposure step; and pattering the conducting layer using the patterned photoresist layer as a mask, thereby forming a capacitor electrode.

Abstract: An ion repulsion structure for a fuse window is provided. The ion repulsion structure includes multi-level metallic layers and a P-type silicon semiconductor substrate having a plurality of wells. The P-type silicon semiconductor substrate includes an N-type well, a P-type well formed in the N-type well and a plurality of P+ type diffusion regions formed in the P-type well. A fuse element is formed on the P-type silicon semiconductor substrate. A fuse window layer is formed over the fuse element. Multi-level metallic layers surrounding the fuse window are formed. A plurality of contact plugs is electrically connected between the P+ type diffusion regions of the semiconductor substrate and the lowest metallic layer. A plurality of via plugs electrically connect the multi-level metallic layers to each other.

Abstract: A method for quickly identifying floating cells by a bit-line coupling pattern (BLCP), an electronic analysis method, identifies floating cells by inputting different background data and inducing net charges from adjacent bit-lines to the bit-lines corresponding to floating cells by coupling parasitic capacitors, wherein the floating results from open bit-line contacts and/or open DRAM cell contacts. Moreover, a method for identifying floating cells according to the invention has the advantages of high efficiency and low cost.

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact.

Abstract: A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed.

Abstract: A method of fabricating a capacitor plate constitutes first providing a substrate. Then, first insulating layer is formed over the substrate. Sequentially, a buffering layer and a second insulating layer, both of which constitute a stacked structure, are formed over the first insulating layer. Next, the stacked structure is patterned into an opening thereby exposing a portion of the first insulating layer therethrough. Subsequently, conducting spacers are formed on the sidewalls of the opening. The second insulating layer is thereafter removed, and simultaneously a portion of the first insulating layer not covered by the buffering layer and the conducting spacers are removed to form a contact window, thereby exposing a portion of the substrate therethrough. Then, a conducting layer is conformably deposited over the substrate, and thereafter etched away until a portion of the buffering layer is exposed. Finally, the exposed buffering layer is removed.

Abstract: The present invention provides a method for fabricating a storage plate of a semiconductor capacitor. A conductive layer is first formed on a semiconductor substrate. A glue layer is formed on the conductive layer. A plurality of micro masking-balls are then spread onto the surface of the glue layer. Using these micro masking-balls as masks, the glue layer is etched to expose a portion surface of the conductive layer. Using the remaining glue layer as a mask, the conductive layer is etched to form a bristle-shaped conductive layer. After that, the glue layer and micro masking-balls are removed, thereby allowing the remaining bristle-shaped conductive layer to form a storage plate of a semiconductor capacitor.

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact.

Abstract: A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers.