Abstract: A method of manufacturing chip resistors has steps of cutting grooves in a substrate, forming through holes, defining chip regions, forming main electrodes, forming resistor layers, forming first protective layers, forming stripped protective layers, forming inner electrodes, removing the stripped protective layers, plating outer electrodes and cutting the substrate. The step of cutting grooves on a substrate includes forming multiple parallel grooves on a substrate. The step of forming through holes includes forming multiple through holes between and across two adjacent grooves on the substrate, and each through hole has smooth inner walls. The step of plating outer electrodes includes plating outer electrodes on the inner electrodes by rack plating. The step of cutting the substrate includes cutting the substrate along the grooves to obtain individual chip resistors.

Abstract: A method of manufacturing chip resistors has steps of cutting grooves on a substrate, forming through holes, defining chip regions, forming main electrodes, forming resistor layers, forming primary protective layers, dividing the substrate into multiple strips, forming inner electrodes, cutting the strips into multiple chip resistor units and plating outer electrodes. The step of cutting grooves on a substrate includes forming multiple grooves parallel to each other on a substrate. The step of forming through holes includes forming multiple through holes between and across each two adjacent grooves on the substrate, and each through hole has smooth inner walls. The step of dividing the substrate into multiple strips includes cutting the substrate along and perpendicular to the through holes. The step of cutting the strips into multiple chip resistor units includes cutting the strips along the grooves into multiple chip resistor units.

Abstract: A substrate for forming passive elements in chip type has a top surface, a thickness, multiple parallel grooves, multiple through holes and multiple chip regions. The parallel grooves are formed on the top surface of the substrate. The through holes are formed between and across two adjacent parallel grooves, and each through hole is separated from other through holes and has smooth inner walls. The chip regions are defined between adjacent through holes and parallel grooves and are arranged in a matrix.

Abstract: A ceramic multilayer capacitor array having a plurality of capacitors in a surface mount compatible package. The array is constructed from a plurality of first dielectric plates, each of which has a first pattern of electrodes, and a plurality of second dielectric plates, each of which has a second pattern of electrodes. The second pattern of electrodes is substantially identical to the first pattern of electrodes, and is shifted with respect to the first pattern of electrodes. Each of the electrodes has at least one tab portion, which extends to at least one of the side faces of the package. Perpendicularly projecting first and second plates, the tab portions of the electrodes in the first plates are free from the tab portions of the electrodes in the second plates.

Abstract: The ceramic multilayer capacitor array of the invention has a plurality of capacitors (1, 2, 3, 4) in a surface mount compatible package (10). The array is constructed from a plurality of first dielectric plates (11), each of which has a first pattern of electrodes (13, 14), and a plurality of second dielectric plates (21), each of which has a second pattern of electrodes (23, 24, 25). The second pattern of electrodes (23, 24, 25) is substantially identical to the first pattern of electrodes (13, 14), and is shifted with respect to it. Each of the electrodes (13, 14, 23, 24, 25) has at least one tab portion (18, 19; 26, 27, 28, 29), which extends to at least one of the side faces (38, 39, 48, 49) of the package (10). Perpendicularly projecting first (11) and second plates (21), the tab portions (18, 19) of the electrodes (13, 14) in the first plates (11) are free from the tab portions (26, 27, 28, 29) of the electrodes (23, 24, 25) in the second plates (21).