Abstract: A method for determining a failure mode with the greatest effect on yield loss in a semiconductor manufacturing process is disclosed. A predetermined number of wafers are processed, and each chip on each wafer is divided into a plurality of regions with each region having a plurality of cells. Electrical tests are performed on each cell, and a region is said to have a failure mode if one cell within the region has that failure mode. The yield loss contribution of a failure mode is determined by considering the yield loss from several wafers having that failure mode as the main failure mode. The yield loss contribution of a failure mode can also be determined by considering the percentage of defective chips on a wafer having that failure mode as the main failure mode. The failure mode with the highest yield loss contribution has the greatest effect on yield loss.

Abstract: A method for identifying failure signatures of semiconductor wafers is disclosed. Testing for obtaining a first set of test data indicative of a failure signature is performed on a number of wafers having circuit patterns thereon. The test data is divided into a first subset of test data associated with a failure signature and a second subset of test data not associated with the failure signature. The set of test data is used to generate coefficients of a discriminant function. Testing is performed on a subsequently manufactured wafer to obtain a second set of test data. The discriminant function is applied to the second set of test data to obtain a discriminant value, and the wafer is identified as having the failure signature when the discriminant value is greater than or equal to a threshold value.