Abstract: To determine when to service a cell queue in an ATM network, a cell scheduler can use an ideal service interval time. The ideal service interval time of each cell queue is the reciprocal of the bandwidth assigned to that cell queue. An interval based cell scheduler is then initialized by setting a time reference to zero and setting a next service time for each queue to the queue's ideal service interval. The cell scheduler then enters a repeating loop. During each iteration of the loop, the first nonempty cell queue having the smallest next service time value is selected. The selected queue is serviced and its next service time is updated by adding its ideal service interval. The time reference value is also updated. If all the queues are empty, then an idle time slot is allowed to pass. The cell queues may consists of queue groups. For example, several queues can be gathered into a queue group that assigned a single ideal service time.

Abstract: A smart antenna system includes: an antenna array including a plurality of antenna elements, and at least one calibration element; a plurality of transceiver units each having a port coupled with an associated one of the antenna elements, a receive port, and a transmit port; a transceiver calibration unit including a port coupled with the calibration element via a coaxial cable, a receive port, and a transmit port; and signal processing means communicatively coupled with each of the receive ports and the transmit ports of each of the transceiver units, and coupled with the calibration receive port and the calibration transmit port of the calibration unit. A transmitter calibration path associated with each antenna element extends from the transmit port of the associated transceiver unit to the associated antenna element, from the associated antenna element to the calibration element, and from the calibration element to the receive port of the calibration unit.

Abstract: A time division duplex switching circuit provides for selectively coupling signals between an antenna and a front stage transceiver circuit. The switching circuit is operative in a transmit mode and in a receive mode, and includes: a transmitter amplifier having an input and an output; a receiver amplifier having an input and an output; a first circulator including a first port coupled for communication with the front stage transceiver, a second port selectively coupled with the output of the receiver amplifier via a first switching, and a third port selectively coupled with the input of the transmitter amplifier via a second switching; and a second circulator including a first port coupled for communication via the antenna, a second port coupled with the input of the receiver amplifier, and a third port coupled with the output of the transmitter amplifier.

Abstract: To determine when to service a cell queue in an ATM network, a cell scheduler can use an ideal service interval time. The ideal service interval time of each cell queue is the reciprocal of the bandwidth assigned to that cell queue. An interval based cell scheduler is then initialized by setting a time reference to zero and setting a next service time for each queue to the queue's ideal service interval. The cell scheduler then enters a repeating loop. During each iteration of the loop, the first nonempty cell queue having the smallest next service time value is selected. The selected queue is serviced and its next service time is updated by adding its ideal service interval. The time reference value is also updated. If all the queues are empty, then an idle time slot is allowed to pass. The cell queues may consists of queue groups. For example, several queues can be gathered into a queue group that assigned a single ideal service time.

Abstract: A parallel CRC remainder coefficient generator (100) and method (1100) are described for providing efficient error detection in a digital data communication system. This method calculates a K-bit CRC remainder m data bits at a time, where m can be less than, equal to, or greater than K, and where the processing of each of the m bits requires a total of j, K-bit table look-ups into a total of j tables of 2.sup.b entries each, where m=jb. It also requires one m-bit exclusive-or operation, a total of (j-1) K-bit exclusive-or operations, and one (K-m)-bit exclusive-or operation if m<K. An implementation of a 16-bit CRC using the new method (700) in a 16-bit DSP processor with m=16, j=2 and b=8 reduces processor loading by 43% relative to the fastest prior art method which uses m=8, j=1, and b=8.