Patents by Inventor Shipra Bhal
Shipra Bhal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907160Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.Type: GrantFiled: August 5, 2022Date of Patent: February 20, 2024Assignee: Analog Devices, Inc.Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
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Publication number: 20220374389Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
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Patent number: 11422969Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.Type: GrantFiled: June 26, 2020Date of Patent: August 23, 2022Assignee: Analog Devices, Inc.Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
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Publication number: 20200327095Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.Type: ApplicationFiled: June 26, 2020Publication date: October 15, 2020Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
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Patent number: 10733141Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.Type: GrantFiled: August 14, 2018Date of Patent: August 4, 2020Assignee: Analog Devices, Inc.Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
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Publication number: 20190303348Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.Type: ApplicationFiled: August 14, 2018Publication date: October 3, 2019Inventors: Manish J. Manglani, Shipra Bhal, Christopher Mayer
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Patent number: 9465754Abstract: A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.Type: GrantFiled: June 28, 2013Date of Patent: October 11, 2016Assignee: Analog Devices, Inc.Inventors: Alexander Leonard, Shipra Bhal, Christopher Mayer
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Patent number: 9124292Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.Type: GrantFiled: November 10, 2014Date of Patent: September 1, 2015Assignee: Analog Devices GlobalInventors: Zhao Li, Shipra Bhal, Kevin Glenn Gard, David Nelson Alldred, Christopher Mayer, Trevor Clifford Caldwell, David J. McLaurin, Victor Kozlov
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Publication number: 20150070200Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.Type: ApplicationFiled: November 10, 2014Publication date: March 12, 2015Applicant: ANALOG DEVICES GLOBALInventors: Zhao Li, SHIPRA BHAL, KEVIN GLENN GARD, DAVID NELSON ALLDRED, CHRISTOPHER MAYER, TREVOR CLIFFORD CALDWELL, DAVID J. McLAURIN, VICTOR KOZLOV
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Publication number: 20150006775Abstract: A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Applicant: Analog Devices, Inc.Inventors: Alexander LEONARD, Shipra BHAL, Christopher MAYER
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Patent number: 8884802Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.Type: GrantFiled: June 18, 2013Date of Patent: November 11, 2014Assignee: Analog Devices TechnologyInventors: Zhao Li, Shipra Bhal, Kevin Glenn Gard, David Alldred, Christopher Mayer, Trevor Clifford Caldwell, David J. McLaurin, Victor Kozlov
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Publication number: 20140266825Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.Type: ApplicationFiled: June 18, 2013Publication date: September 18, 2014Applicant: Analog Devices TechnologyInventors: Zhao Li, Shipra Bhal, Kevin Glenn Gard, David Alldred, Christopher Mayer, Trevor Clifford Caldwell, David J. McLaurin, Victor Kozlov